MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 567

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

E.5 AC Characteristics
MC68F375
REFERENCE MANUAL
NOTES:
Num
1
2
3
4
5
6
1. All internal registers retain data at 0 Hz.
2. Assumes that V
3. Assumes that V
4. Cold start is measured from V
5. Internal VCO frequency (f
6. Determined by internal loss-of-clock oscillator operating frequency.
7. Jitter is the average deviation from programmed frequency measured over the specified interval at maximum f sys . Measure-
8. This parameter is periodically sampled rather than 100% tested.
9. Design information only, not tested.
stable.
by V
that is not in the synthesizer feedback loop. When X = 0, the divider is enabled, and f
disabled, and f
ments are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into
the PLL circuitry via power supply pins and variation in crystal oscillator frequency increase the stability percentage for a given
interval. The use of reference frequencies and system frequencies very much different than those shown here may require dif-
ferent XFC filter values than shown in
PLL Reference Frequency Range
System Frequency
On-Chip PLL System Frequency:
PLL Lock Time
VCO frequency
Limp Mode Clock Frequency
CLKOUT Jitter
DD
ramp-up. Lock time is measured from VDD at specified minimum to RESET negated.
Indirect:
Fast reference mode
Slow reference mode
Fast reference mode
Slow reference mode
External Clock Operation
Changing W or Y in SYNCR or exiting from LPSTOP
Warm Start-up
Cold start (fast mode only)
Slow Reference Mode (32.768 kHz):
Short term (5 s interval)
Long term (500 s interval)
Fast Reference Mode (4.194 MHz):
Short term (3 system clocks)
Long term (2 ms interval)
sys
DDSYN
DDSYN
(V
= f
9
5
7,8,9
VCO
DDL
is stable, that an external filter is attached to the XFC pin, and that the crystal oscillator is stable, followed
3
and V
1
/2. X must equal one when operating at maximum specified f
VCO
and V
Characteristic
Freescale Semiconductor, Inc.
DD
) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a divide-by-two circuit
9
DDSYN
For More Information On This Product,
are stable, that an external filter is attached to the XFC pin, and that the crystal oscillator is
Table E-4 Clock Control Timing
DDSYN
6,9
4
ELECTRICAL CHARACTERISTICS
and V
4.3.7.2 Phase Comparator and Filter
Go to: www.freescale.com
= 3.3 Vdc 10%, V
DD
at specified minimum to RESET negated.
Rev. 25 June 03
2
SS
Symbol
= 0 Vdc, T
J
f
f
f
VCO
f
t
limp
CLK
sys
lpll
ref
to maintain optimum jitter performance.
Minimum
A
(f
ref
4(f
-0.05
-0.01
= T
sys
-0.5
-1.0
sys
DC
0.1
25
dc
—
—
—
—
)/128
1
ref
.
= f
L
)
to T
VCO
/4. When X = 1, the divider is
H .)
Maximum
2(f
f
sys
sys
33.6
33.6
33.6
33.6
0.05
0.01
0.5
1.0
50
20
50
75
max/2
6
max)
MOTOROLA
Unit
MHz
MHz
MHz
MHz
KHz
ms
%
E-5