MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 448

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.4.4.2 SDATA — SASM Data Register A
S14DATA — SASM Data Register A
S16DATA
S18DATA
S20DATA
13.4.4.3 SICB — SASM Status/Interrupt Control Register B
MC68F375
REFERENCE MANUAL
Bit(s)
MSB
15
3:2
1:0
U
RESET:
4
SDATA is the 16-bit read-write register associated with channel A. In IC mode, SDATA
contains the last captured value. In the OC, OCT and OP modes, it is loaded with the
value of the next output compare. SDATA is not affected by reset.
This register contains the control and status bits for SASM channel B. The bits it con-
tains are identical to those in SICA, with the exception of the IL[2:0], IARB3 and IEN
which apply to both channels simultaneously and which are included only in SICA. For
descriptions of the bits, please refer to
trol Register
14
U
MODE1,
MODE0
EDOUT
Name
—
13
U
Edge detect and output level. In IC mode, the EDOUT bit is used to select the edge that will trig-
ger the input capture circuitry. In OC mode, the EDOUT bit is used to latch the value to be output
to the pin on the next output compare match or when the FORCE bit is set. Internal synchroni-
zation ensures that the correct level appears on the output pin when a new value is written to
EDOUT and FORCE is set at the same time. Reading EDOUT returns the previous value writ-
ten. In OCT mode, the EDOUT bit has no effect. However, the force function is still available and
will force the value of the EDOUT bit to appear on the output pin. In OP mode, the value of the
EDOUT bit is output to the corresponding pin. Reading EDOUT returns the previous value writ-
ten.
0 = Input capture on falling edge.
1 = Input capture on rising edge.
Reserved
SASM operating mode select. These control bits select the mode of operation of the SASM
channel, as shown in the following table. MODE1 and MODE0 are cleared by reset.
00 = Input capture (IC).
01 = Output port (OP).
10 = Output compare (OC
11 = Output compare and toggle (OCT)
A).
12
U
MSB
Table 13-7 SICA Bit Settings (Continued)
Freescale Semiconductor, Inc.
11
U
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
10
U
Go to: www.freescale.com
U
9
Rev. 25 June 03
U
8
13.4.4.1 SICA — SASM Status/Interrupt Con-
U
7
Description
U
6
U
5
U
4
LSB
U
3
U
2
0xYF F272,
0xYF F2A2
0xYF F282
0xYF F292
MOTOROLA
U
1
13-22
LSB
U
0