MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 102

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.3.8.6 Low Power Operation
MC68F375
REFERENCE MANUAL
In order to reset the ports to their post reset state listed in
and the reset signal must be present. The clocks are generated with the SCIM2E volt-
age controlled oscillator (VCO). The VCO is biased to operate at approximately eight
KHz whenever the crystal oscillator is not detected. This feature causes the VCO to
start before the crystal oscillator. (See
TICS
Only single byte or aligned word writes on the IMB to the RAM module will be guaran-
teed to complete without data corruption for synchronous resets. A long-word write, a
misaligned operand write, a write to a peripheral module other than the RAM or a read
cycle are not guaranteed. External writes are also guaranteed to complete, provided
the external configuration logic on the data bus is conditioned by R/W. Asynchronous
reset sources usually indicate a catastrophic failure and require the reset control logic
to assert reset to the system immediately.
Low power operation is initiated by the CPU32. To reduce power consumption selec-
tively, the CPU32 can set the STOP bits in each module configuration register. To
minimize overall microcontroller power consumption, the CPU32 can execute the
LPSTOP instruction which causes the SCIM2E to turn off the system clock.
A loss of clock will be recognized while the part is in low power stop, unless the RC
oscillator is disabled. If it is disabled, external RESET will re-enable it so that RESET
will be recognized. If a loss of clock occurs in LPSTOP mode and RSTEN=0, the part
will continue to operate normally on the alternate clock. LPSTOP can then be exited
normally, either by an interrupt request or by external RESET. If RSTEN=1 in LPSTOP
mode, the loss of clock event will cause reset. For more information, see
Power Stop
for the exact frequencies.)
Mode.
NOTES:
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
PQS0, PQS1, PQS2
1. Each port requires approximately 4 clocks to assume their
Freescale Semiconductor, Inc.
post reset state. The VCO startup time is no more than 15
msec after VDD reaches minimum value.
For More Information On This Product,
PQA, PQB
Table 4-8 Port Reset Condition
TPU3
Port
A
G
B
H
E
F
C
1
Go to: www.freescale.com
Rev. 25 June 03
APPENDIX E ELECTRICAL CHARACTERIS-
Output (PC[6:2, 0]) are driven high
State of Pins after Reset
Input
Input
Input
Input
Input
Input
Input
Input
Input
Table
4-8, an internal clock
MOTOROLA
4.4.9 Low
4-20