MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 197

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.10.3.4 Continuous-Scan Modes
MC68F375
REFERENCE MANUAL
single-scan enable bit. Software may set the single-scan enable bit again to allow
another scan of queue 1 to be initiated during the next open gate.
If the gate closes before queue 1 completes execution, the current CCW completes,
execution of queue 1 stops, the single-scan enable bit is cleared, and the PF1 bit is
set. Software can read the CWPQ1 to determine the last valid conversion in the queue.
Software must set the single-scan enable bit again and should clear the PF1 bit before
another scan of queue 1 is initiated during the next open gate. The start of queue 1 is
always the first CCW in the CCW table.
Interval Timer Single-Scan Mode. Both queues can use the periodic/interval timer in
a single-scan queue operating mode. The timer interval can range from 128 to 128K
QCLK cycles in binary multiples. When the interval timer single-scan mode is selected
and the software sets the single-scan enable bit in QACR1(2), the timer begins count-
ing. When the time interval elapses, an internal trigger event is created to start the
queue and the QADC64 begins execution with the first CCW.
The QADC64 automatically performs the conversions in the queue until a pause or an
end-of-queue condition is encountered. When a pause occurs, queue execution stops
until the timer interval elapses again, and queue execution continues. When the queue
execution reaches an end-of-queue situation the single-scan enable bit is cleared.
Software may set the single-scan enable bit again, allowing another scan of the queue
to be initiated by the interval timer.
The interval timer generates a trigger event whenever the time interval elapses. The
trigger event may cause the queue execution to continue following a pause, or may be
considered a trigger overrun. Once the queue execution is completed, the single-scan
enable bit must be set again to enable the timer to count again.
Normally, only one queue will be enabled for interval timer single-scan mode and the
timer will reset at the end-of-queue. However, if both queues are enabled for either sin-
gle-scan or continuous interval timer mode, the end-of-queue condition will not reset
the timer while the other queue is active. In this case, the timer will reset when both
queues have reached end-of-queue.
The interval timer single-scan mode can be used in applications which need coherent
results, for example:
When the application software wants to execute multiple passes through a sequence
of conversions defined by a queue, a continuous-scan queue operating mode is
• When it is necessary that all samples are guaranteed to be taken during the same
• When the interrupt rate in the periodic timer continuous-scan mode would be too
• In sensitive battery applications, where the single-scan mode uses less power
scan of the analog pins.
high.
than the software initiated continuous-scan mode.
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
5-21