MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 100

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.3.7.3 Lock Detect Circuit
4.3.7.4 Clock Control Circuit
4.3.7.5 Loss Of Clock Detect Circuit (LOC)
4.3.8 Basic Operation
MC68F375
REFERENCE MANUAL
The clock generator subsystem on the MC68F375 also includes an improved lock
detect circuit. This lock detect does not depend on frequency over-shoot as did the
original circuit. It is also more precise than the original circuit. Basic operation is based
on two counters and a “frequency match” requirement. When the VCO feedback fre-
quency ramps to within approximately 3.5% of the reference frequency, a count-down
time-out is initiated. At the end of that period, the PLL is considered locked and the
SLOCK bit is set in the SYNCR register. This same logic will reset the SLOCK bit if the
VCO feedback frequency drifts outside of approximately ± 3.5% range. The actual trip
points for going into and out of lock depend on the phase relationship of the reference
frequency and the VCO feedback frequency.
The clock control circuit generates the following system clock signals:
The loss of clock (LOC) feature is designed to detect the condition in which the SCIM2
SCIMCLK system clock falls in frequency to a range between 20 KHz and 150 Hz. The
LOC circuit uses an independent, free-running RC oscillator as a time base to monitor
the system clock. The LOC circuit is used as a system protection feature to monitor
the operation of the crystal reference for the PLL, or the presence of an external clock
signal.
The SCIM2 internal system clock, SCIMCLK, is monitored by a loss-of-clock sub-
system. SCIMCLK remains running in LPSTOP at the PLL frequency if STSCIM=1, or
at the crystal frequency if STSCIM=0, or at the external clock frequency if the part is
in External Clock mode. The LOC detector should always be triggered if SCIMCLK
falls below 150 Hz, and should never be triggered if SCIMCLK is running above 20
KHz. This specified range provides a sufficiently large window of uncertainty to com-
pensate for variations in the RC oscillator frequency due to processing and operating
conditions.
• EXTCLK is the external system clock which is driven out on the CLKOUT pin. This
• ICLOCK is the internal module system clock. This clock is used by all of the inter-
• SCLOCK is the SCIM2 module’s primary clock. This clock is used by all sections
• SCIMCLK: This is the SCIM2’s secondary system clock which is used by sections
signal is also used to generate the E clock which is used by the chip selects.
nal modules of the MCU except for the SCIM2. This clock is stopped in LPSTOP
mode.
of the SCIM2 except those that must continue to operate in LPSTOP. This clock
is stopped in LPSTOP mode.
of the SCIM2 which continue to operate in LPSTOP mode, such as timers in the
system protection block.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
4-18