MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 219

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

QASR0 — QADC64 Status Register
RESET:
MC68F375
REFERENCE MANUAL
Bit(s)
MSB
CF1
15
15
14
13
12
11
10
0
The four flag bits and the two trigger overrun bits are cleared by writing a zero to the
bit after the bit was previously read as a one.
PF1
14
0
Name
TOR1
TOR2
CF1
PF1
CF2
PF2
CF2
13
0
Queue 1 completion flag. CF1 indicates that a queue 1 scan has been completed. CF1 is set by
the QADC64 when the conversion is complete for the last CCW in queue 1, and the result is
stored in the result table.
0 = Queue 1 scan is not complete.
1 = Queue 1 scan is complete.
Queue 1 pause flag. PF1 indicates that a queue 1 scan has reached a pause. PF1 is set by the
QADC64 when the current queue 1 CCW has the pause bit set, the selected input channel has
been converted, and the result has been stored in the result table.
0 = Queue 1 has not reached a pause.
1 = Queue 1 has reached a pause.
Queue 2 completion flag. CF2 indicates that a queue 2 scan has been completed. CF2 is set by
the QADC64 when the conversion is complete for the last CCW in queue 2, and the result is
stored in the result table.
0 = Queue 2 scan is not complete.
1 = Queue 2 scan is complete.
Queue 2 pause flag. PF2 indicates that a queue 2 scan has reached a pause. PF2 is set by the
QADC64 when the current queue 2 CCW has the pause bit set, the selected input channel has
been converted, and the result has been stored in the result table.
0 = Queue 2 has not reached a pause.
1 = Queue 2 has reached a pause.
Queue 1 trigger overrun. TOR1 indicates that an unexpected queue 1 trigger event has occurred.
TOR1 can be set only while queue 1 is active.
A trigger event generated by a transition on ETRIG1/ETRIG2 may be recorded as a trigger over-
run. TOR1 can only be set when using an external trigger mode. TOR1 cannot occur when the
software initiated single-scan mode or the software initiated continuous-scan mode is selected.
0 = No unexpected queue 1 trigger events have occurred.
1 = At least one unexpected queue 1 trigger event has occurred.
Queue 2 trigger overrun. TOR2 indicates that an unexpected queue 2 trigger event has occurred.
TOR2 can be set when queue 2 is in the active, suspended, and trigger pending states.
A trigger event generated by a transition depending on the value of TRG in QACR or ETRIG1/
ETRIG2 or by the periodic/interval timer may be recorded as a trigger overrun. TOR2 can only
be set when using an external trigger mode or a periodic/interval timer mode. Trigger overruns
cannot occur when the software initiated single-scan mode and the software initiated continuous-
scan mode are selected.
0 = No unexpected queue 2 trigger events have occurred.
1 = At least one unexpected queue 2 trigger event has occurred.
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
PF2
12
0
Freescale Semiconductor, Inc.
TOR1 TOR2
11
0
For More Information On This Product,
Table 5-16 QASR0 Bit Settings
10
0
Go to: www.freescale.com
9
0
Rev. 25 June 03
8
0
QS
7
0
Description
6
0
5
0
4
0
3
0
CWP
2
0
0xYF F410
MOTOROLA
1
0
5-43
LSB
0
0