MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 396

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.6.6.1 Program Sequence
MC68F375
REFERENCE MANUAL
The CMFI EEPROM module requires a sequence of writes to the high voltage control
registers (CMFICTL1 and CMFICTL2) and to the program page buffer(s) in order to
enable the high voltage to the array or shadow information for program operation. The
required program sequence follows.
1. Write PROTECT = 0 to disable protection on the CMFI EEPROM array.
2. Write PAWS to 0b100, write NVR = 1, write GDB = 1.
3. Set the initial pulse width bit settings per
4. Write SES = 1 in the CMFICTL2 register. This step can be done with the same
5. Programming writes. Write to the 64-byte array locations to be programmed.
6. Write EHV = 1 in the CMFICTL2 register. If a program buffer has not received
Technique to Determine SCLKR, CLKPE, and
timing control fields for a program pulse to the CMFICTL1 register. Write
BLOCK[7:0] to select the array blocks to be programmed and PE = 0 in the
CMFICTL2 register.
write in step 2 but is split out as a separate step in the sequence for looping.
This shall update the programming page buffer(s) with the information to be
programmed. Only the last write to each word within the program page buffer
shall be saved for programming. All accesses of the array after the first write
shall be to the same block offset address (IADDR[14|13:6]) regardless of the
address provided. Thus the locations accessed after the first programming
write are limited to the page locations to be programmed. Off page read access-
es of the CMFI array after the first programming write are program margin reads
see section
All program page buffers share the same block offset address (IAD-
DR[14|13:6]) stored in the BIU. The block offset address is extracted from the
address of the first programming write. To select the CMFI EEPROM array
block(s) that will be programmed, the program page buffers use the CMFI EE-
PROM array configuration and BLOCK[7:0]. Subsequent writes fill in the pro-
gram page buffers using the block address to select the program page buffer
and the page word address (IADDR[5:2]) to select the word in the page buffer.
The array configuration and BLOCK[7:0] determine which blocks are pro-
grammed simultaneously.
If the PROTECT bit is set then the CMFI EEPROM array will not be
programmed. Also, if PEEM = 0, no programming voltages will be
applied to the array and if B0EM = 0, no programming voltages will
be applied to block 0.
Do not select the block bits of blocks not currently being programmed.
10.6.6.2 Program Margin
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
WARNING
WARNING
Reads.
Table
CLKPM, write the pulse width
10-6. Using section
MOTOROLA
10.4.9 A
10-26