MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 212

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

PORTQA — Port QA Data Register
PORTQB — Port QB Data Register
QADC64INT — QADC64 Interrupt Register
5.12.3 Port A/B Data Register
MC68F375
REFERENCE MANUAL
RESET:
PQA7
AN59
served
Bit(s)
14:12
MSB
ANALOG CHANNEL:
MULTIPLEXED ADDRESS OUTPUTS:
10:8
MSB
15
7:0
Re-
U
15
11
15
MULTIPLEXED ANALOG
RESET:
0
QADC64 ports A and B are accessed through two 8-bit port data registers (PORTQA
and PORTQB).
PQA6 PQA5
AN58
14
U
INPUTS:
14
0
Name
IRL1
IRL2
IVB
—
—
AN57
13
IRL1
U
13
0
Reserved
Interrupt level for queue 1. A value of 00000 provides an interrupt level of 0; 0b111 provides a
level interrupt. All interrupts are presented on the IMB3. Interrupt level priority software deter-
mines which level has the highest priority request.
Reserved
Interrupt level for queue 2. A value of 00000 provides an interrupt level of 0; 0b111 provides a
level interrupt. All interrupts are presented on the IMB3. Interrupt level priority software deter-
mines which level has the highest priority request.
Interrupt vector base. Initialization software inputs the upper six IVB bits in the interrupt register.
During interrupt arbitration, the vector provided to the bus master by the QADC is made up of the
upper six IVB bits , plus two low-order bits provided to the QADC to identify one of four QADC
interrupt requests. The interrupt vector number is independent of the interrupt level and the inter-
rupt arbitration number. A 0x0F vector number corresponds to the uninitialized interrupt vector.
After reset, the lower byte of the interrupt register reads as 0x0F. Once the IVB field is written,
the two least significant bits always read as zeros.
PQA4
AN56
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
12
U
12
0
PQA3
Freescale Semiconductor, Inc.
AN55
served
11
U
Re-
11
For More Information On This Product,
Table 5-8 QADC64INT Bit Settings
0
PQA2 PQA1 PQA0 PQB7 PQB6 PQB5 PQB4 PQB3 PQB2 PQB1 PQB0
AN54
MA2
10
U
10
0
Go to: www.freescale.com
AN53
MA1
U
9
IRL2
Rev. 25 June 03
9
0
AN52
MA0
U
8
8
0
AN51
U
7
Description
7
0
AN50
U
6
6
0
AN49
U
5
5
0
AN48
U
4
4
0
IVB
AN3
ANz
U
3
3
0
AN2
ANy
U
2
2
0
0xYF F406
0xYF F404
MOTOROLA
AN1
ANx
1
0
U
1
LSB
ANw
LSB
AN0
5-36
0
0
U
0