MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 434

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MC68F375BGMZP33

Manufacturer Part Number
MC68F375BGMZP33
Description
IC MPU 32BIT 33MHZ 217-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68F375BGMZP33

Processor Type
M683xx 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
217-PBGA
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
256 KB
Data Ram Size
10 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
48
Number Of Timers
16
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
No

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MC68F375
REFERENCE MANUAL
Bit(s)
14:12
9:8
6:3
2:0
15
11
10
7
DRV[A:B]
CLK[2:0]
IARB3
Name
IL[2:0]
COF
IN
Counter overflow flag. This status flag bit indicates whether or not a counter overflow has oc-
curred. An overflow is defined to be the transition of the counter from 0xFFFF to 0x0000. If the
IL field is non-zero, an interrupt request is generated when the COF bit is set. The flag clearing
mechanism will work only if no flag setting event occurs between the read and write operations;
if a COF setting event occurs between the read and write operations, the COF bit will not be
cleared.
0 = Counter overflow has not occurred.
1 = Counter overflow has occurred.
Interrupt level. The three interrupt level bits are read/write control bits that select the priority level
of interrupt requests made by the FCSM. These bits can be read or written at any time and are
cleared by reset.
000 = Interrupt disabled
001 = Interrupt level 1 (lowest)
010 = Interrupt level 2
011 = Interrupt level 3
100 = Interrupt level 4
101 = Interrupt level 5
110 = Interrupt level 6
111 = Interrupt level 7 (highest)
The read/write IARB3 bit works in conjunction with the IARB[2:0] field in the BIUSM module con-
figuration register. Each module that generates interrupt requests on the IMB must have a
unique value in the arbitration field (IARB). This interrupt arbitration identification number is used
to arbitrate for the IMB when modules generate simultaneous interrupts of the same priority.
Reserved
Drive time base bus. DRVA and DRVB are read/write bits that control the connection of the FCSM
to the time base buses A and B. These bits are cleared by reset. It is recommended that the two
time base buses not be driven at the same time.
00 = Neither time base bus A nor time base bus B is driven.
01 = Time base bus B is driven
10 = Time base bus A is driven
11 = Both time base bus A and time base bus B are driven
Input pin status. This read-only status bit reflects the logic state of the FCSM input pin CTMC.
Writing a ‘zero’ or a ‘one’ to this bit has no effect. Reset has no effect on this bit.
Reserved
Counter clock select. These read/write control bits select one of six internal clock signals
(PCLKx) or one of two external conditions on the input pin (rising edge or falling edge). The max-
imum frequency of the external clock signals is f
000 = Prescaler output 1 (/2 or /3)
001 = Prescaler output 2 (/4 or /6)
010 = Prescaler output 3 (/8 or /12)
011 = Prescaler output 4 (/16 or /24)
100 = Prescaler output 5 (/32 or /48)
101 = Prescaler output 6 (/64 to /512 or /96 to /768)
110 = CTMC pin input, negative edge
111 = CTMC pin input, positive edge
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Table 13-3 FMSMSIC Bit Settings
Go to: www.freescale.com
Rev. 25 June 03
Description
SYS
/4.
MOTOROLA
13-8

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