MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 455

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.5.2.5 Output Compare (OCB and OCAB) Modes
MC68F375
REFERENCE MANUAL
OC mode is selected by making MODE[3:0] = 010x. The MODE0 bit controls the set-
ting criteria for the FLAG bit, i.e. when a compare occurs only on channel B or when a
compare occurs on either channel (see
rupt Control
This mode allows the DASM to perform four different output functions:
In this mode the leading and trailing edges of variable width output pulses are gener-
ated by calculated output compare events occurring on channels A and B,
respectively. OC mode may also be used to perform a single output compare function,
similar to the M68HC11 timer, or may be used as an output port bit.
In this mode, channel B is accessed via register B2. Register B1 is not used and is not
accessible to the user. Both channels work together to generate one ‘single shot’ out-
put pulse signal. Channel A defines the leading edge of the output pulse, while channel
B defines the trailing edge of the pulse. FLAG setting can be done when a compare
occurs on channel B only or when a compare occurs on either channel (as defined by
the MODE0 bit in the DASMSIC register).
When this mode is first selected, both comparators are disabled. Each comparator is
enabled by writing to its data register; it remains enabled until the next successful com-
parison is made on that channel, whereupon it is disabled. The values stored in
registers A and B are compared with the count value on the selected time base bus
when their corresponding comparators are enabled.
• Single-shot output pulse (two edges), with FLAG set on the second edge.
• Single-shot output pulse (two edges), with FLAG set on both edges.
• Single-shot output transition (one edge).
• Output port pin, with output compare function disabled.
DASMA captured value
Notes:
Time base bus
Input signal
B1 value
B2 value
Mode selection; EDPOL = 0
FLAG bit
Register).
1. These values are accessible to the software.
2. These values are internal and are not accessible.
1
2
1
Figure 13-9 DASM Input Capture Example
Freescale Semiconductor, Inc.
0x0500
0xxxxx
0xxxxx
0xxxxx
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Go to: www.freescale.com
0x1000
0x1000
0x1000
0xxxxx
A
FLAG reset
by software
Rev. 25 June 03
0x1100
13.5.5.1 DASMSIC — DASM Status/Inter-
0x1250
0x1250
0x1250
0x1000
A
FLAG reset
by software
0x1525
0x16A0
0x16A0
0x16A0
0x1250
FLAG reset
by software
A
MOTOROLA
13-29