MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 85

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
9:8
3:0
15
14
13
12
11
10
7
6
5
4
The SCIMMCR register controls the system configuration. SCIMMCR can be read or
written at any time, except for the module mapping (MM) bit, which can only be written
once after reset, and the reserved bit, which is read-only. Writes have no effect.
FRZSW
SLOWE
FRZBM
EXOFF
Name
CPUD
SHEN
SUPV
RWD
IARB
ABD
MM
—
External clock off.
0 = The CLKOUT pin is driven during normal operation.
1 = The CLKOUT pin is placed in a high-impedance state.
Freeze software enable. Enables or disables the software watchdog and periodic interrupt timer
during background debug mode when FREEZE is asserted.
0 = Enables the software watchdog and periodic interrupt timer when FREEZE is asserted.
1 = Disables the software watchdog and periodic interrupt timer when FREEZE is asserted.
Freeze bus monitor enable.
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
CPU development support disable. CPUD is cleared to zero when the MCU is in an expanded
mode, and set to one in single-chip mode.
0 = Instruction pipeline signals available on pins IPIPE and IFETCH.
1 = Pins IPIPE and IFETCH placed in high-impedance state unless a breakpoint occurs.
Reserved
Slow mode enable. Control bit which forces pins on the chip to operate in fast mode regardless
of how they are set up from the controlling module. Slow mode is enabled by setting this bit.
0 = Pins setup by the controlling module to operate in slow mode will operate in fast mode.
1 = Pins will operate at the normal speed controlled by the module.
Show cycle enable. The SHEN field determines how the external bus is driven during internal
transfer operations. A show cycle allows internal transfers to be monitored externally.
3
can occur. To prevent bus conflict, external devices must not be selected during show cycles.
Supervisor/user data space. The SUPV bit places the SCIM2E global registers in either super-
visor or user data space.
0 = Registers access controlled by the SUPV bit accessible in either supervisor or user mode.
1 = Registers access controlled by the SUPV bit restricted to supervisor access only.
Module mapping
0 = Internal modules are addressed from 0x7FF000 – 0x7FFFFF.
1 = Internal modules are addressed from 0xFFF000 – 0xFFFFFF.
Address Bus Disable. ABD is cleared to zero when the MCU is in an expanded mode, and set
to one in single-chip mode. ABD can be written only once after reset.
0 = Pins ADDR[2:0] operate normally.
1 = Pins ADDR[2:0] are disabled.
Read/write disable. RWD is cleared to zero when the MCU is in an expanded mode, and set to
one in single-chip mode. RWD can be written only once after reset.
0 = R/W signal operates normally
1 = R/W signal placed in high-impedance state.
Each module that can generate interrupts, including the SCIM2E, has an IARB field. Each IARB
field can be assigned a value from 0x0 to 0xF. During an interrupt acknowledge cycle, IARB per-
mits arbitration among simultaneous interrupts of the same priority level. The reset value of the
SCIM2 IARB field is 0xF, the highest priority. This prevents SCIM2 interrupts from being discard-
ed during system initialization.
indicates whether show cycle data is driven externally, and whether external bus arbitration
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
Table 4-1 SCIMMCR Bit Descriptions
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
Description
MOTOROLA
Table 4-
4-3