MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 137

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.7.2 Reset Exception Processing
4.7.3 Reset Source Summary
MC68F375
REFERENCE MANUAL
The CPU32 processes resets as a type of asynchronous exception. An exception is
an event that preempts normal processing and can be caused by internal or external
events. Exception processing makes the transition from normal instruction execution
to execution of a routine that deals with an exception. Each exception has an assigned
vector that points to an associated handler routine. These vectors are stored in the
exception vector table. The exception vector table consists of 256 four-byte vectors
and occupies 1024 bytes of address space. The CPU32 uses vector numbers to cal-
culate displacement into the table. Refer to
information.
Reset is the highest-priority CPU32 exception. Unlike all other exceptions, a reset
occurs at the end of a bus cycle and not at an instruction boundary. Handling resets in
this way prevents write cycles in progress at the time the reset signal is asserted from
being corrupted. However, any processing in progress is aborted by the reset excep-
tion and cannot be restarted. Only essential reset tasks are performed during
exception processing. Other initialization tasks must be accomplished by the excep-
tion handler routine.
SCIM2E reset control logic determines the cause of a reset, synchronizes request sig-
nals to CLKOUT, and asserts reset control logic. All resets are gated by CLKOUT.
Asynchronous resets can occur on any clock edge and are assumed to be cata-
strophic. Synchronous resets are timed to occur at the end of bus cycles. When a
synchronous reset is detected, the SCIM2E bus monitor is automatically enabled. If
the bus cycle during which a synchronous reset is detected does not terminate nor-
mally, the bus monitor will terminate the cycle and allow the reset to proceed.
4-22
Software watchdog
is a summary of reset sources.
Loss of clock
Power on
External
Type
Test
Halt
External circuitry is required to disable external bus configuration
logic until DS and R/W are negated to ensure that bus cycles in
progress at the time RESET is asserted complete correctly.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
Assertion of RESET pin
Rising voltage on V
Timeout of software watchdog
Halt monitor (e.g. double bus fault)
Reference failure caught by loss of clock detector
Test submodule
For More Information On This Product,
Table 4-22 Reset Source Summary
Go to: www.freescale.com
Rev. 25 June 03
DD
Source
NOTE
3.9 Exception Processing
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Timing
MOTOROLA
for more
Table
4-55