MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 132

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.6.6 External Bus Arbitration
MC68F375
REFERENCE MANUAL
During dynamically-sized 8-bit transfers, external bus activity may not stop at the next
cycle boundary. Occurrence of a bus error while HALT is asserted causes the CPU32
to initiate a retry sequence.
When the MCU completes a bus cycle while the HALT signal is asserted, the data bus
goes into a high-impedance state and the AS and DS signals are driven to their inac-
tive states. Address, function code, size, and read/write signals remain in the same
state.
The halt operation has no effect on bus arbitration. However, when external bus arbi-
tration occurs while the MCU is halted, address and control signals go into a high-
impedance state. If HALT is still asserted when the MCU regains control of the bus,
address, function code, size, and read/write signals revert to the previous driven
states. The MCU cannot service interrupt requests while halted.
The MCU bus design provides for a single bus master at any one time. Either the MCU
or an external device can be master. Bus arbitration protocols determine when an
external device can become bus master. Bus arbitration requests are recognized dur-
ing normal processing, HALT assertion, and when the CPU32 has halted due to a
double bus fault.
The MCU bus controller manages bus arbitration signals so that the MCU has the low-
est priority. External devices that need to obtain the bus must assert bus arbitration
signals in the sequences described in the following paragraphs.
Systems that include several devices that can become bus master require external cir-
cuitry to assign priorities to the devices, so that when two or more external devices
attempt to become bus master at the same time, the one having the highest priority
becomes bus master first. The protocol sequence for assuming bus mastership from
the MCU is:
BR can be asserted during a bus cycle or between cycles. BG is asserted in response
to BR. To guarantee operand coherency, BG is only asserted at the end of operand
transfer.
If more than one external device can be bus master, required external arbitration must
begin when a requesting device receives BG. An external device must assert BGACK
when it assumes mastership, and must maintain BGACK assertion as long as it is bus
master.
Two conditions must be met for an external device to assume bus mastership. The
device must receive BG through the arbitration process, and BGACK must be inactive,
1. An external device asserts the bus request signal (BR).
2. The MCU asserts the bus grant signal (BG) to indicate that the bus is available.
3. An external device asserts the bus grant acknowledge (BGACK) signal to indi-
cate that it has assumed bus mastership.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
4-50