MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 450

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Channel A comprises one 16-bit data register and one 16-bit comparator. Channel B
also appears to the user to consist of one 16-bit data register and one 16-bit compar-
ator, however, internally, channel B has two data registers B1 and B2, and the
operating mode determines which register is accessed by the software:
Register contents are always transferred automatically at the correct time so that the
minimum pulse (measurement or generation) is just one time base bus count. The A
and B data registers are always read/write registers, accessible via the CTM’s sub-
module bus.
In the input capture modes, the edge detect circuitry triggers a capture whenever a ris-
ing or falling edge (as defined by the EDPOL bit) is applied to the input pin. The signal
on the input pin is Schmitt triggered and synchronized with the system clock (f
• In the input capture modes (IPWM, IPM and IC), registers A and B2 are used to
• In the output compare modes (OCA and OCAB), registers A and B2 are used to
• In the output pulse width modulation mode (OPWM), registers A and B1 are used
hold the captured values; in these modes, the B1 register is used as a temporary
latch for channel B.
define the output pulse; register B1 is not used in these modes.
as primary registers and hidden register B2 is used as a double buffer for channel
B.
MODE3 MODE2
select
Control register bits
Bus
16-bit comparator B
MODE1 MODE0
16-bit comparator A
Freescale Semiconductor, Inc.
16-bit register A
16-bit register B1
16-bit register B2
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Figure 13-6 DASM Block Diagram
BSL
Go to: www.freescale.com
2 time base buses
Rev. 25 June 03
Submodule bus
FORCA
flip-flop
Output
FLAG
FORCB
Control register bits
IL2
Interrupt
Output
control
EDPOL
detect
buffer
Edge
WOR
IL1
TBBA
TBBB
IL0
IN
IARB3
I/O pin
MOTOROLA
SYS
13-24
).