MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 78

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

3.10.7.3 Current Instruction Program Counter (PCC)
3.10.8 Returning from BDM
3.10.9 Serial Interface
MC68F375
REFERENCE MANUAL
flow of a program under development. Changing the RPC to an odd value will cause
an address error when normal mode prefetching begins.
The PCC holds a pointer to the first word of the last instruction executed prior to tran-
sition into background mode. Due to instruction pipelining, the instruction pointed to
may not be the instruction which caused the transition. An example is a breakpoint on
a released write. The bus cycle may overlap as many as two subsequent instructions
before stalling the instruction sequencer. A breakpoint asserted during this cycle will
not be acknowledged until the end of the instruction executing at completion of the bus
cycle. PCC will contain 0x00000001 if BDM is entered via a double bus fault immedi-
ately out of reset.
BDM is terminated when a resume execution (GO) or call user code (CALL) command
is received. Both GO and CALL flush the instruction pipeline and refetch instructions
from the location pointed to by the RPC.
The return PC and the memory space referred to by the status register SUPV bit reflect
any changes made during BDM. FREEZE is negated prior to initiating the first pre-
fetch. Upon negation of FREEZE, the serial subsystem is disabled, and the signals
revert to IPIPE/IFETCH functionality.
Communication with the CPU32 during BDM occurs via a dedicated serial interface,
which shares pins with other development features.
the interface. The BKPT signal becomes the serial clock (DSCLK); serial input data
(DSI) is received on IFETCH, and serial output data (DSO) is transmitted on IPIPE.
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSOR UNIT
Go to: www.freescale.com
Rev. 25 June 03
Figure 3-10
is a block diagram of
MOTOROLA
3-24