MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 473

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
2:0
4
3
CLK[2:0]
Name
POL
EN
Output pin polarity control. The POL bit is a control bit that allows the software to set the polarity
of the PWM output signal. It works in conjunction with the EN bit and controls whether the
PWMSM drives the output pin with the true or inverted value of the output flip-flop, see
13-16.
Enable control. The EN bit is a control bit that allows the software to enable and disable the
PWMSM as required.
0 = Disable the PWMSM and stop generation of PWM output pulses.
1 = Enable the PWMSM and start generation of PWM output pulses.
While the PWMSM is disabled (EN = 0):
When the EN bit is changed from zero to one:
While EN is set, the PWMSM generates continuously a pulse width modulated output signal
based on the data in PWMA2 and PWMB2 (which are updated via PWMA1 and PWMB2 each
time a period is completed). To prevent unwanted glitches on the output waveform when dis-
abling the PWMSM, the EN bit should not be cleared by the software until one period has been
output as a 0% pulse (PWMB2 = 0x0000)
Clock rate selection. The CLK bits are control bits that allow the software to select one of the
eight counter clock sources coming from the PWMSM prescaler. These bits can be changed by
the software at any time.
Table 13-15 PWMSIC Bit Settings (Continued)
– The output flip-flop is held reset and the level on the output pin is set to one or zero
– The PWMSM’s divide-by-256 prescaler is held in reset,
– The counter stops incrementing and is held equal to 0x0001,
– The comparators are disabled,
– And the PWMA1 and PWMB1 registers permanently transfer their contents to the buffer
– The output flip-flop is set to start the first pulse,
– The PWMSM’s divide-by-256 prescaler is released,
– The counter is released and starts to increment from 0x0001,
– And the FLAG bit is set (to indicate that PWMA1 and PWMB1 can be updated with new
according to the state of the POL bit,
registers (PWMA2 and PWMB2, respectively).
values of period and pulse width.
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Go to: www.freescale.com
Table 13-17
Rev. 25 June 03
shows the counter clock sources and rates in detail.
Description
MOTOROLA
Table
13-47