MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 437

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.3.2.2 Using the MCSM as a Free-Running Counter
13.3.3 MCSM Clock Sources
13.3.4 MCSM External Event Counting
13.3.5 The MCSM Time Base Bus Driver
13.3.6 MCSM interrupts
MC68F375
REFERENCE MANUAL
bits to zero, thereby preventing a signal on the CTML pin from loading the counter reg-
ister until EDGEN and EDGEP have been initialized by the software. The modulus
load input pin CTML is Schmitt triggered and synchronized to the system clock (f
The MCSM is a modulus counter. However it can be made to behave like a free-run-
ning counter by loading the modulus register with the value 0x0000.
The User can choose from eight software selectable counter clock sources:
The clock source is selected by the CLK[2:0] bits in the MCSM status, interrupt and
control register MCSMSIC (see
Register). When the CLK[2:0] bits are being changed, internal circuitry ensures that
spurious edges occurring on the CTMC pin do not affect the MCSM. The clock input
pin CTMC is Schmitt triggered and is synchronized with the system clock (f
When an external clock source (on the CTMC input pin) is selected, the MCSM is in
the event counter mode. The counter can simply count the number of events occurring
on the input pin. Alternatively, the MCSM can be programmed to generate an interrupt
when a predefined number of events have been counted; this is done by presetting the
counter with the two’s complement value of the desired number of events. When using
the external clock source, the maximum external guaranteed frequency is f
The DRVA and DRVB bits in the MCSMSIC register select the time base buses to be
driven (see
A valid MCSM interrupt can be generated when the COF bit in the MCSMSIC register
is set as a result of the counter overflowing. If the interrupt priority level of the MCSM
is non-zero, as defined by the three IL bits in the MCSMSIC register, a valid interrupt
request will occur on the IMB.
• Six prescaler outputs (PCLKx)
• Input pin rising edge detection on the input pin CTMC
• Input pin falling edge detection on the input pin CTMC
The read-only IN1 bit of the MCSMSIC reflects the state of the input
pin CTML.
The read-only IN2 bit of the MCSMSIC register reflects the state of
the input pin CTMC.
13.3.9 MCSMSIC — MCSM Status/Interrupt/Control
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Go to: www.freescale.com
13.3.9 MCSMSIC — MCSM Status/Interrupt/Control
Rev. 25 June 03
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