MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 328

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
NOTES:
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SCIM2E configuration
—
—
S
S
S
register (SCIMMCR).
0xYFF08A
0xYFF09A
0xYFF0A0
0xYFF0A2
0xYFF0A4
0xYFF0A6
0xYFF080
0xYFF082
0xYFF084
0xYFF086
0xYFF088
0xYFF090
0xYFF092
0xYFF094
0xYFF096
0xYFF098
Address
—
—
Freescale Semiconductor, Inc.
1
For More Information On This Product,
Table 7-10 TouCAN Register Map
15
See
See
Receive Error Counter (RXECTR)
Control Register 0 (CANCTRL0)
CAN 2.0B CONTROLLER MODULE
See
See
See
See
Divider Register (PRESDIV)
Table 7-13
Table 7-17
Control and Prescaler
See
7.8.10 Receive Buffer 15 Mask Registers
7.8.10 Receive Buffer 15 Mask Registers
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7.8.9 Receive Buffer 14 Mask Registers
7.8.9 Receive Buffer 14 Mask Registers
bit descriptions.
bit descriptions.
TouCAN Module Configuration Register (TCNMCR)
TouCAN Interrupt Configuration Register (CANICR)
Table 7-26
descriptions.
Receive Buffer 15 FMask – High (RX15MASKHI)
Receive Buffer 14 Mask – Low (RX14MASKLO)
Receive Buffer 15 Mask – Low (RX15MASKLO)
Receive Buffer 14 Mask – High (RX14MASKHI)
Rev. 25 June 03
Receive Global Mask – High (RXGMASKHI)
Receive Global Mask – Low (RXGMASKLO)
and
and
Free-Running Timer Register (TIMER)
See
See
See
See
See
See
See
Error and Status Register (ESTAT)
Table 7-16
Table 7-18
TouCAN Test Register (TTR)
for bit
Table 7-11
Table 7-19
Table 7-20
Table 7-20
Table 7-21
Table 7-24
Table 7-25
Interrupt Masks (IMASK)
Interrupt Flags (IFLAG)
Reserved
Reserved
for
for
8 7
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
Transmit Error Counter (TXECTR)
Control Register 1 (CANCTRL1)
Control Register 2 (CTRL2)
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
MOTOROLA
0
7-22