MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 378

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.4.1 CMFI EEPROM Module Control Block Addressing
MC68F375
REFERENCE MANUAL
Control bits in these registers are provided to control array operation, programming
and erasing.
Some of the control registers have shadow information words which physically exist in
a spare CMFI EEPROM row. On master reset, some of the registers and fields within
certain registers are loaded with default reset information from the shadow information
words. Writing to a register does not alter the contents of the corresponding shadow
information word. Using the address of the corresponding control register, the shadow
information word is programmed in the same manner as a location in the CMFI
EEPROM array. When data is latched into the programming latches while program-
ming a shadow information word, it will not be written to the register itself. Data which
is programmed into the CMFIMCR, CMFIBAR or CMFICTL register’s shadow informa-
tion word will not be copied into the register until the next master reset.
programmed. The registers that are loaded from shadow information words during
master reset are identified in the individual register field and control bit descriptions.
The shadow information words are erased whenever the low block (block 0) of the
array is erased.
The module control block is addressed by comparing the module control mapping
(IMODMAP) to IADDR[23] while IADDR[22:5] are decoded by the CMFI EEPROM
module. If the CMFI EEPROM control block address is decoded, the CMFI EEPROM
module will assert the address acknowledge (IAACKB) signal. The value of
IADDR[22:5] is defined for each device that has a CMFI EEPROM module. These bits
are fixed for a particular device (MCU or peripheral), and are specified by Motorola.
The value of the module control mapping (IMODMAP) is specified by a control bit in
the module configuration register, see
ter
by IADDR[4:0]. The control block is restricted to supervisor data space (IFC[2:0] =
0b101). Any other address space read or write of the registers will not assert address
acknowledge. See
The last write to a programming buffer prior to setting EHV determines the value to be
• The module configuration register (CMFIMCR)
• Array base address register (CMFIBAR)
• CMFI EEPROM high voltage control register (CMFICTLx).
(CMFIMCR). The exact register addressing within the control block is determined
Table 10-3
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
for control register offset addresses.
Rev. 25 June 03
10.4.3 CMFI EEPROM Configuration Regis-
MOTOROLA
10-8