MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 291

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

QSCI1CR — QSCI1 Control Register
6.8.7.9 Internal Loop Mode
6.9 SCI Queue Operation
6.9.1 Queue Operation of SCI1 for Transmit and Receive
6.9.2 Queued SCI1 Status and Control Registers
6.9.2.1 QSCI1 Control Register
MC68F375
REFERENCE MANUAL
RESET:
Bit(s)
15:12
MSB
15
11
10
0
The LOOPS bit in SCCxR1 controls a feedback path in the data serial shifter. When
LOOPS is set, the SCI transmitter output is fed back into the receive serial shifter. TXD
is asserted (idle line). Both transmitter and receiver must be enabled before entering
loop mode.
The SCI1 serial module allows for queueing on transmit and receive data frames. In
the standard mode, in which the queue is disabled, the SCI1 operates as previously
defined (i.e. transmit and receive operations done via SC1DR). However, if the SCI1
queue feature is enabled (by setting the QTE and/or QRE bits within QSCI1CR) a set
of 16 entry queues is allocated for the receive and/or transmit operation. Through soft-
ware control the queue is capable of continuous receive and transfer operations within
the SCI1 serial unit.
The SCI1 queue uses the following registers:
• QSCI1 control register (QSCI1CR, address offset 0x28)
• QSCI1 status register (QSCI1SR, address offset 0x2A)
14
QTPNT
QTPNT
0
QTHFI
QBHFI
Name
13
0
Queue transmit pointer. QTPNT is a 4-bit counter used to indicate the next data frame within the
transmit queue to be loaded into the SC1DR. This feature allows for ease of testability. This field
is writable in test mode only; otherwise it is read-only.
Receiver queue top-half full interrupt. When set, QTHFI enables an SCI1 interrupt whenever the
QTHF flag in QSCI1SR is set. The interrupt is blocked by negating QTHFI. This bit refers to the
queue locations SCRQ[0:7].
0 = QTHF interrupt inhibited
1 = Queue top-half full (QTHF) interrupt enabled
Receiver queue bottom-half full interrupt. When set, QBHFI enables an SCI1 interrupt whenever
the QBHF flag in QSCI1SR is set. The interrupt is blocked by negating QBHFI. This bit refers to
the queue locations SCRQ[8:15].
0 = QBHF interrupt inhibited
1 = Queue bottom-half full (QBHF) interrupt enabled
12
0
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
QTH-
11
For More Information On This Product,
FI
0
Table 6-31 QSCI1CR Bit Settings
QBH-
10
FI
0
Go to: www.freescale.com
QTHE
9
0
I
Rev. 25 June 03
QB-
HEI
8
0
7
0
0
Description
QTE
6
0
QRE
5
0
QTW
E
4
0
3
0
2
0
0xYF FC28
QTSZ
MOTOROLA
1
0
6-57
LSB
0
0