MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 182

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.3.7 Dedicated Analog Supply Pins
5.3.8 External Digital Supply Pin
5.3.9 Digital Supply Pins
5.4 QADC64 Bus Interface
5.5 Module Configuration
5.5.1 Low-Power Stop Mode
MC68F375
REFERENCE MANUAL
filtering, which increases reference voltage precision and stability, and subsequently
contributes to a higher degree of conversion accuracy.
V
Dedicated power is required to isolate the sensitive analog circuitry from the normal
levels of noise present on the digital power supply.
Each port A pin includes a digital output driver, an analog input signal path, and a dig-
ital input synchronizer. The V
port A pins. V
V
digital MCU modules.
The QADC64 supports 8-bit, 16-bit, and 32-bit data transfers, at even and odd
addresses. Coherency of results read, (ensuring that all results read were taken con-
secutively in one scan) is not guaranteed. For example, if two consecutive 16-bit
locations in a result area are read, the QADC64 could change one 16-bit location in
the result area between bus cycles. There is no holding register for the second 16-bit
location. All read and write accesses that require more than one 16-bit access to com-
plete occur as two or more independent bus cycles. Depending on bus master
protocol, these accesses could include misaligned and 32-bit accesses.
Normal reads from and writes to the QADC64 require two clock cycles. However, if the
CPU tries to access locations that are also accessible to the QADC64 while the
QADC64 is accessing them, the bus cycle will require additional clock cycles. The
QADC64 may insert from one-to-four wait states in the process of a CPU read from,
or write to, such a location.
The QADC64 module configuration register (QADC64MCR) defines freeze and stop
mode operation, supervisor space access, and interrupt arbitration priority. Unimple-
mented bits read zero and writes have no effect. QADC64MCR is typically written once
when software initializes the QADC64, and not changed thereafter. Refer to
QADC64 Module Configuration Register
When the STOP bit in QADC64MCR is set, the clock signal to the A/D converter is dis-
abled, effectively turning off the analog circuitry. This results in a static, low power
consumption, idle condition. Low-power stop mode aborts any conversion sequence
in progress. Because the bias currents to the analog circuits are turned off in low-
DDA
DD
and V
and V
SS
SSA
provide the power for the digital portions of the QADC64, and for all other
DDH
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
pins supply power to the analog subsystems of the QADC64 module.
provides the supply level for the drivers on port A pins.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
SSE
Rev. 25 June 03
pin provides the ground level for the drivers on the
for register and bit descriptions.
MOTOROLA
5.12.1
5-6