MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 208

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.11.5 Interrupt Vectors
MC68F375
REFERENCE MANUAL
The same interrupt priority level can be assigned to more than one module. For exam-
ple, the QADC and the queued serial module (QSM) can both be assigned priority five.
If the QADC and the QSM request interrupt service simultaneously, then the interrupt
arbitration (IARB) fields in the respective module configuration registers are used to
determine which module is serviced first.
The IARB field is essentially a second-level priority in case of a tie. Each module that
can request interrupt service has an IARB field. Arbitration is per formed by means of
serial contention of IARB field bit values. Arbitration always takes place, even when a
single source requests service.
IARB fields contain four bits. An IARB value of 0b1111 has the highest arbitration pri-
ority, and 0b0001 has the lowest. If a module with an IARB field value of 0b0000
requests interrupt service, the bus master processes a spurious interrupt exception
because the module requesting the interrupt service cannot confirm that it made the
request. Initialization software must assign each IARB field a unique non-zero value in
order to implement the arbitration scheme. If two or more modules are assigned the
same non-zero IARB field value, operation is undefined when interrupts of the same
priority level are recognized.
When the QADC is the only module with an interrupt request pending at the level being
acknowledged, or when the QADC IARB value is higher than that of other modules
with requests pending at the acknowledged level, the QADC responds to the interrupt
acknowledge cycle with an 8-bit interrupt vector number. The CPU uses the vector
number to calculate a displacement into the exception vector table, then uses the vec-
tor at that location to jump to an interrupt service routine.
The interrupt vector base (IVB) field establishes the six high-order bits of the 8-bit inter-
rupt vector number, and the QADC provides two low-order bits which correspond to
one of the four internal QADC interrupt sources.
interrupt vector, and lists the binary coding of the two low-order bits for the four QADC
interrupt sources.
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
Figure 5-11
shows the format of the
MOTOROLA
5-32