MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 75

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

3.10.4.1 External BKPT Signal
3.10.4.2 BGND Instruction
3.10.4.3 Double Bus Fault
3.10.4.4 Peripheral Breakpoints
3.10.5 Entering BDM
MC68F375
REFERENCE MANUAL
Table 3-4
cases. As shown in
BDM.
Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM
is disabled, a breakpoint exception (vector 0x0C) is acknowledged. The BKPT input
has the same timing relationship to the data strobe trailing edge as does read cycle
data. There is no breakpoint acknowledge bus cycle when BDM is entered.
An illegal instruction, 0x4AFA, is reserved for use by development tools. The CPU32
defines 0x4AFA (BGND) to be a BDM entry point when BDM is enabled. If BDM is
disabled, an illegal instruction trap is acknowledged.
The CPU32 normally treats a double bus fault, (an exception that occurs while stack-
ing for another exception) as a catastrophic system error and halts. When this
condition occurs during initial system debug (a fault in the reset logic), further debug-
ging is impossible until the problem is corrected. In BDM, the fault can be temporarily
bypassed, so that the origin of the fault can be isolated and eliminated.
CPU32 peripheral breakpoints are implemented in the same way as external break-
points — peripherals request breakpoints by asserting the BKPT signal. Consult the
appropriate peripheral user’s manual for additional details on the generation of
peripheral breakpoints.
When the processor detects a breakpoint or a double bus fault, or decodes a BGND
instruction, it suspends instruction execution and asserts the FREEZE output. This is
the first indication that the processor has entered BDM. Once FREEZE has been
asserted, the CPU enables the serial communication hardware and awaits a
command.
summarizes the processing of each source for both enabled and disabled
BGND Instruction
Double Bus Fault
BKPT Instruction
Source
BKPT
Freescale Semiconductor, Inc.
Table
For More Information On This Product,
Table 3-4 BDM Source Summary
CENTRAL PROCESSOR UNIT
3-4, the BKPT instruction never causes a transition into
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Opcode Substitution/
Illegal Instruction
Rev. 25 June 03
BDM Enabled
Background
Background
Background
Breakpoint Exception
Opcode Substitution/
Illegal Instruction
Illegal Instruction
BDM Disabled
Halted
MOTOROLA
3-21