MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 418

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

ROMMCR — ROM Module Configuration Register
MC68F375
REFERENCE MANUAL
STOP
MSB
Bit(s)
14:13
NOTES:
15
0
15
12
11
10
RESET:
1. The default state of this bit is defined by customer specified options.
2. Indicates bits protected by LOCK and STOP.
3. Indicates bits protected by LOCK only.
RESERVED
14
0
BOOT
Name
STOP
LOCK
EMUL
—
13
0
BOOT LOCK EMUL
Inverted state of D[14]. If STOP is set to a 1 by the inverted D[14] during master reset, the array
may be re-enabled by clearing STOP after master reset. If bootstrap mode is enabled, (BOOT
= 0), clearing STOP will not cause the ROM to enter bootstrap mode. The STOP bit must be set
in order to change the value of the array base address (ROMBAH, ROMBAL), the state of the
EMUL control bit, or the value of the ASPC field in ROMMCR. Clearing the STOP bit also deac-
tivates emulation mode, but does not disable it.
0 = The ROM module is in normal mode of operation.
1 = Causes the ROM module to enter STOP mode.
Reserved
Bootstrap enable. At mask programming time, the ROM module may be specified to function as
a bootstrap ROM after RESET or only as a ROM array at a specified base address. The BOOT
bit is forced to its default reset state by master reset. The default reset state of the BOOT bit is
specified by the user at mask programming time and is programmed on the same mask layer as
the contents of the array.
0 = ROM module will respond to the bootstrap addresses after RESET.
1 = ROM module will not respond to the bootstrap addresses after RESET.
Lock registers. Once the LOCK bit is set, via an IMB3 write, it cannot be cleared again until after
a master reset. If the default reset state is 1, all registers and bits protected by the LOCK
bit can never be changed. The LOCK bit is forced to its default reset state by master reset. The
default reset state of the LOCK bit is specified by the user at mask programming time and is pro-
grammed on the same mask layer as the contents of the array. To ensure that inadvertent re-
configuration of the ROM cannot occur, the user’s initialization program should always write this
bit to a one to invoke the write lock mechanism, if it’s default reset state is 0.
0 = Write lock is disabled.
1 = Write-locked registers are protected.
Emulation mode. Emulation mode allows the ROM array to be emulated externally, with access
controlled by the ROM module BIU. Bootstrap operation is not affected by emulation mode, nor
is it emulated. Emulation mode may be entered by writing EMUL to a 1. The STOP bit in the
ROMMCR must be a 1 in order to change the state of the EMUL bit by writing to it via the IMB3.
In emulation mode the ROM will not respond to an array address with IAACKB, however, it will
respond to control register accesses. Instead of responding with IAACKB to array addresses, it
will assert the ICSMB line on the IMB3, allowing the device’s external bus interface to assert an
external chip select and run a special external bus cycle which is terminated by the ROM assert-
ing IDTACKB on the IMB3. The ROM will assert IDTACKB after the proper number of WAIT
states, as specified in the WAIT field of the ROMMCR register. The ROM module will not drive
the IMB3 data lines however. Data must be provided by an external device at the proper time.
See
0 = The ROM module is in normal mode of operation.
1 = Causes the ROM module to enter emulation mode.
12
U
1
4.7.8.6 Emulation Mode
Freescale Semiconductor, Inc.
U
11
1
For More Information On This Product,
Table 12-2 ROMMCR Bit Settings
10
0
Go to: www.freescale.com
ASPC[1:0]
MASK ROM MODULE
U
9
1
Rev. 25 June 03
Selection.
U
8
1
,2
WAIT[1:0}
U
7
1
Description
U
6
1
3
5
0
4
0
RESERVED
3
0
2
0
0xYF F820
MOTOROLA
1
0
LSB
12-4
0
0