MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 206

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.11.1 Interrupt Operation
5.11.1.1 Polled and Interrupt-Driven Operation
5.11.2 Interrupt Sources
MC68F375
REFERENCE MANUAL
same priority. The QADC is configured to support interrupt acknowledge (IACK) cycles
and vector generation.
Figure 5-10
QADC inputs can be monitored by polling or by using interrupts. When interrupts are
not needed, software can disable the pause and completion interrupts and monitor the
completion flag and the pause flag for each queue in the status register (QASR). In
other words, flag bits can be polled to determine when new results are available.
Table 5-5
1 and queue 2 activity. If interrupts are enabled for an event, the QADC requests inter-
rupt service when the event occurs. Using interrupts does not require continuously
polling the status flags to see if an event has taken place. However, status flags must
be cleared after an interrupt is serviced, in order to disable the interrupt request. In
both polled and interrupt-driven operating modes, status flags must be re-enabled
after an event occurs. Flags are re-enabled by clearing appropriate QASR bits in a par-
ticular sequence. The register must first be read, then zeros must be written to the
flags that are to be cleared. If a new event occurs betwe en the time that the register
is read and the time that it is written, the associate d flag is not cleared.
The QADC includes four sources of interrupt service requests, each of which is sepa-
rately enabled. Each time the result is written for the last conversion command word
(CCW) in a queue, the completion flag for the corresponding queue is set, and when
PIE1
CIE1
PIE2
CIE2
CF1
CF2
PF1
PF2
displays the status flag and interrupt enable bits which correspond to queue
displays the QADC64 interrupt flow.
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
CONVERSION COMPLETE INTERRUPT
CONVERSION COMPLETE INTERRUPT
Figure 5-10 QADC64 Interrupt Flow Diagram
Freescale Semiconductor, Inc.
CONVERSION COMPLETE FLAG
CONVERSION COMPLETE FLAG
CONVERSION PAUSE ENABLE
CONVERSION PAUSE ENABLE
CONVERSION PAUSE FLAG
CONVERSION PAUSE FLAG
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
ENABLE
ENABLE
QUEUE 1
QUEUE 2
(IRL1)
(IRL2)
GENERATOR
INTERRUPT
INTERRUPT
CONTROL
MOTOROLA
IRQ[7:0]
5-30