MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 415

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

12.1 Introduction
12.2 Mask Programmable Options
MC68F375
REFERENCE MANUAL
The mask ROM module for the Modular Embedded Controller Family is designed to
be used with the family’s inter-module bus (IMB3) and consequently any CPU capable
of operating on it. The mask ROM module implementation for the MC68F375 is 8,192
(8K) bytes.
The array is arranged in a 16-bit configuration and is accessed via the device’s internal
bus. It may be read as either bytes, aligned words or misaligned words. Access times
depend on the number of WAIT states specified at mask programming time, but can
be as fast as 2 system clocks for byte and aligned word access. It is also capable of
responding to back-to-back IMB3 accesses to provide 2 bus cycle (4 system clocks)
access for aligned long word or misaligned word operations, and 3 bus cycles for mis-
aligned long words. The ROM module may be used to contain program information
only, or both program and data information.
The ROM module can be used as fast access memory to contain program code which
must execute at high speed, or which gets executed often. Operating system kernels
and standard subroutines benefit from this fast access time. It can also be pro-
grammed to insert WAIT states to accommodate migration from slower external
development memory to on-chip ROM, without the need for retiming the system. The
ROM module may be configured to generate bootstrap information on RESET, without
the array being mapped to location 0x000000.
The ROM module can also operate in a special emulation mode, which simplifies emu-
lation of the internal ROM by an external device, when used with a system integration
module which makes use of the ICSMB IMB3 line.
Along with the contents of the ROM array, several configuration options must be spec-
ified by the customer. These options are mask programmed on the same mask layer
as the contents of the array. The options comprise:
• Default reset state of the base address of the array.
• Default reset state of the BOOT control bit which determines if the ROM responds
• Default reset state of the LOCK control bit which controls write access to config-
• Default reset state of the WAIT field which controls the number of clocks for ROM
• Default reset state of the ASPC field which specifies the address space of the
to bootstrap addresses.
uration registers.
accesses.
ROM array.
Freescale Semiconductor, Inc.
For More Information On This Product,
MASK ROM MODULE
Go to: www.freescale.com
MASK ROM MODULE
SECTION 12
Rev. 25 June 03
MOTOROLA
12-1