MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 207

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.11.3 Interrupt Priority
5.11.4 Interrupt Arbitration
MC68F375
REFERENCE MANUAL
enabled, an interrupt request is generated. In the same way, each time the result is
written for a CCW with the pause bit set, the queue pause flag is set, and when
enabled, an interrupt request is generated.
Table 5-5
1 and queue 2 activity. The pause and complete interrupts for queue 1 and queue 2
have separate interrupt vector levels, so that each source can be separately serviced.
Interrupt priority is determined with a three-bit interrupt priority mask that is located in
the bus master condition code register or status register. The interrupt priority mask
can have eight possible values, from 0b000 to 0b111.
There are seven levels of interrupt priority, one to seven, each corresponding to a par-
ticular interrupt request signal. The bus master compares the priority of each interrupt
service request to the mask value. Interrupt request levels greater than the mask value
are accepted; interrupt request levels less than or equal to the mask value are
ignored, except for the nonmaskable level seven interrupt request, which is serviced
even if the bus master interrupt mask value is seven.
The values contained in the IRL1 and IRL2 fields in the interrupt register (QADC64INT)
determine the priority of QADC interrupt service requests. A value of 0b000 in either
field disables the interrupts associated with that field. IRL1 determines the priority of
both queue 1 interrupt sources. IRL2 determines the priority of both queue 2 interrupt
sources. As a result, queue 1 and queue 2 can have different priorities in the overall
interrupt hierarchy of the MCU. The QADC also has an internal interrupt request pri-
oritization. Queue1 interrupt requests are higher in priority than queue 2 requests, and
completion flag requests ar e higher in priority than pause requests.
After queue 1 or queue 2 issues an interrupt service request, the bus master performs
an interrupt acknowledge cycle. During the interrupt acknowledge cycle, the bus mas-
ter identifies the interrupt request level being acknowledged by placing it on the
address bus. The QADC compares the acknowledged interrupt level with IRL1 and
IRL2 values, and responds if the values match.
Queue 1
Queue 2
Queue
displays the status flag and interrupt enable bits which correspond to queue
Table 5-5 QADC64 Status Flags and Interrupt Sources
Result written for the last CCW in queue 1
Result written for a CCW with pause bit set in
queue 1
Result written for the last CCW in queue 2
Result written for a CCW with pause bit set in
queue 2
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
For More Information On This Product,
Queue Activity
Go to: www.freescale.com
Rev. 25 June 03
Status Flag
CF1
CF2
PF1
PF2
Interrupt Enable Bit
CIE1
PIE1
CIE2
PIE2
MOTOROLA
5-31