MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 149

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
DATA[7:3] select in a contiguous fashion whether ADDR[23:19]/CS[10:6] serve as
high-order address lines or chip selects.
between these pins.
DATA[15:12] allow implementation dependent disabling of on-chip ROM and/or flash
EEPROM modules.
by these pins.
Operation in 8-bit expanded mode is selected when BERR = 1 and DATA1 = 1 at the
release of RESET. In this configuration, ADDR[18:11]/PA[7:0] and ADDR[10:3]/
PB[7:0] become part of the address bus, and only DATA[15:8]/PG[7:0] are used for
the data bus. The ABD, RWD, and CPUD bits in SCIMMCR are clear, enabling
ADDR[2:0], R/W, and the instruction tracking pins (IPIPE/DSO and IFETCH/DSI),
respectively. Ports A, B, and G are unavailable in 8-bit expanded mode, and
DATA[7:0]/PH[7:0] serve as port H discrete I/O pins only. All remaining SCIM2E pins
are configured as shown in
DATA7
1
1
1
1
1
0
NOTES:
Select Pin
Table 4-29 Reset Configuration for MC68F375 Memory Modules
DATA14
DATA15
DATA10,
DATA13
1. The ROM can be disabled if the STOP shadow bit is programmed to one or if DATA14 is
2. The CMFI array is disabled if its STOP shadow bit is programmed to one or if DATA15 is
low at the rising edge of RESET.
low at the rising edge of RESET.
DATA6
Data Bus Pins at Reset
X
1
1
1
1
0
1
2
Edge of RESET
State of Select
DATA5
Table 4-28 Reset Pin Function of CS[10:6]
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Pin at Rising
Freescale Semiconductor, Inc.
X
X
Table 4-29
1
1
1
0
For More Information On This Product,
0
1
0
1
0
1
DATA4
Table
X
X
X
1
1
0
Go to: www.freescale.com
shows which modules on the MC68F375 are affected
Rev. 25 June 03
DATA3
4-30.
X
X
X
X
1
0
All four 32-Kbyte CMFI FLASH blocks disabled
All four 32-Kbyte CMFI FLASH blocks enabled
All four 32-Kbyte FLASH arrays disabled
All four 32-Kbyte FLASH arrays enabled
8-Kbyte Masked ROM array disabled
8-Kbyte Masked ROM array enabled
Table 4-28
ADDR23
ADDR23 ADDR22 ADDR21 ADDR20 ADDR19
CS10/
CS10
CS10
CS10
CS10
CS10
Memory Modules Affected
CMFI/ROM emulation mode
CMFI/ROM normal mode
Chip-Select/Address Bus Pin Function
ADDR22
ADDR22 ADDR21 ADDR20 ADDR19
CS9/
CS9
CS9
CS9
CS9
shows the reset correspondence
ADDR21
ADDR21 ADDR20 ADDR19
CS8/
CS8
CS8
CS8
ADDR20
ADDR20 ADDR19
CS7/
CS7
CS7
ADDR19
ADDR19
MOTOROLA
CS6/
CS6
4-67