MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 397

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
10. If the margin read is successful, then write SES = 0 in the CMFCTL register,
11. If more information needs to be programmed, go back to step 2.
7. Read the CMFICTL1 register until HVS = 0.
8. Write EHV = 0 in CMFICTL2.
9. Program Verify. Read the words of the pages that are being programmed.
a. Write new pulse width parameters (if required per
b. Write new values for PAWS, NVR, and GDB (if required per
c. Go back to step 6 to apply additional programming pulses.
a programming write no programming voltages will be applied to the corre-
sponding word in the array. Also, at this point writes to the program page buffers
are disabled until SES has been cleared and set.
These are program margin reads, see section
Reads. If any bit is a 1 after reading all of the locations that are being pro-
grammed go to step 5. If all the locations verify as programmed go to step 9.
that is being programmed after reading a non-programmed bit. The first location
must be a location with IADDR[5] = 0; while, the second must use IADDR[5] =
1. Also, after a location has been fully verified (all bits are programmed) it is not
necessary to verify the location as no further programming voltages will be ap-
plied to the drain of the corresponding bits.
otherwise do the following:
To reduce the time for verification, read only two locations in each array block
CLKPE, CLKPM.
After a program pulse, read at least one location with IADDR[5] = 0
and one location with IADDR[5] = 1 on each programmed page. Fail-
ure to do so may result in the loss of information in the CMFI
EEPROM array. While this will not physically damage the array it will
require that a full erase of all blocks being programmed be done
before the CMFI EEPROM can be used reliably.
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
WARNING
10.6.6.2 Program Margin
Table
10-6) - SCLKR,
Table
MOTOROLA
10-6).
10-27