MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 181

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.3.3 External Trigger Input Pins
5.3.4 Multiplexed Address Output Pins
5.3.5 Multiplexed Analog Input Pins
5.3.6 Voltage Reference Pins
MC68F375
REFERENCE MANUAL
The QADC64 has two external trigger pins (ETRIG[2:1]). Each of the two external trig-
ger pins is associated with one of the scan queues. When a queue is in external trigger
mode, the corresponding external trigger pin is configured as a digital input.
In non-multiplexed mode, the 16 channel pins are connected to an internal multiplexer
which routes the analog signals into the A/D converter.
In externally multiplexed mode, the QADC64 allows automatic channel selection
through up to four external 1-of-8 multiplexer chips. The QADC64 provides a 3-bit mul-
tiplexed address output to the external multiplexer chips to allow selection of one of
eight inputs. The multiplexed address output signals MA[2:0] can be used as multiplex
address output bits or as general-purpose I/O.
When externally multiplexed mode is enabled, MA[2:0] are used as the address inputs
for up to four 1-of-8 multiplexer chips (for example, the MC14051 and the
MC74HC4051). Since MA[2:0] are digital outputs in multiplexed mode, the software
programmed input/output direction and data for these pins in DDQA[2:0], DDRQA, and
PQA[2:0] is ignored, and the value for MA[2:0] is taken from the currently executing
CCW.
In externally multiplexed mode, four of the port B pins are redefined to each represent
a group of eight input channels. Refer to
The analog output of each external multiplexer chip is connected to one of the AN[w,
x, y, z] inputs in order to convert a channel selected by the MA[2:0] multiplexed
address outputs.
V
arating the reference inputs from the power supply pins allows for additional external
RH
and V
RL
are the dedicated input pins for the high and low reference voltages. Sep-
Multiplexed Analog Input
NOTES:
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
1. If the on-chip multiplexer is enabled, ANw and ANx are used as inputs
2. If the on-chip AMUX is enabled, then AN2 and AN3 should be read as
Table 5-1 Multiplexed Analog Input Channels
for the AMUX outputs.
channels AN16 and AN17.
Freescale Semiconductor, Inc.
ANw
ANx
ANy
ANz
For More Information On This Product,
1
2
2
1
Go to: www.freescale.com
Rev. 25 June 03
Even numbered channels from 16 to 30
Odd numbered channels from 17 to 31
Even numbered channels from 0 to 14
Odd numbered channels from 1 to 15
Table
5-1.
Channels
MOTOROLA
5-5