MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 600

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

BLC 8-12
Block
block diagrams
BME 4-25
BMT 4-25
BOFFINT 7-32
Boundary conditions 5-17
BQ2 5-17, 5-41
BR 4-50, 4-65, 4-77, 4-78
BR 4-49
Branch latch control (BLC) 8-12
Break frame 6-51
Breakpoint
BSA 3-20
BSL
Bus
BUSY 7-5, 7-15
BYP 5-13, 5-49
Bypass mode 5-13
MC68F375
REFERENCE MANUAL
size (BLKSZ) 4-78
CPSM 13-53
DASM 13-24
FCSM 13-5
MCSM 13-9
PWMSM 13-39
SASM 13-15
SASM channel A 13-16
acknowledge cycle 4-43
asserted flag (BKPT) 8-13
flag (PCBK) 8-13
hardware breakpoints 4-43
instruction 3-19
mode selection 4-68
operation 4-45
software breakpoints 4-43
bit in SICA 13-21
arbitration
arbitration for a single device 4-51
cycle
error
grant (BG). See BG 4-50
grant acknowledge (BGACK). See BGACK 4-50
monitor 4-25
off interrupt
request (BR). See BR 4-50
state analyzer (BSA) 3-20
encoding 4-79
timing diagrams
regular 4-39
termination sequences 4-46
exception processing 4-48
signal (BERR) 4-48
signal (BERR). See BERR 4-25
timing of 4-48
external enable (BME) 4-25
timeout period 4-25
timing (BMT) 4-25
(BOFFINT) 7-32
active E-14
idle E-15
Freescale Semiconductor, Inc.
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Rev. 25 June 03
INDEX
BYTE (upper/lower byte option) 4-81, 4-83
C (carry) flag 3-6
CAN2.0B
CANCTRL0 7-26
CANCTRL1 7-27
CANCTRL2 7-29
CANICR 7-25
CCL 8-12
CCR 3-6, 4-71
CCW 5-1, 5-48
CF1 5-43
CF2 5-43
CFSR 8-15
CH 8-14, 8-17, 8-18
CHAN 5-49
changing mode
CHANNEL 8-15
Channel
CHBK 8-13
Chip-select
CIBV 8-14
CIE1 5-39
CIE2 5-41
CIER 8-14, 8-18
system 7-3
DASM 13-25
SASM 13-17
assignments
conditions latch (CCL) 8-12
interrupt
invalid 5-49
number (CHAN) 5-49
orthogonality 8-3
priority registers 8-17
register breakpoint flag (CHBK) 8-13
reserved 5-49
address compare logic 4-79
assertion 4-73
base address registers (CSBAR) 4-78
block (SCIM2) 4-1
circuit block diagram 4-75
operation 4-84
option registers (CSOR) 4-80
pin assignment registers (CSPAR) 4-75, 4-77
reset operation 4-85
signals for interrupt acknowledge cycle termination
timing diagram E-16
multiplexed 5-50
nonmultiplexed 5-50
base vector (CIBV) 8-14
enable
request level (CIRL) 8-14
status (CH) 8-18
reset values 4-86
reset values 4-86
field encoding 4-77
/disable field (CH) 8-14
4-84
–C–
MOTOROLA
Index-2