MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 25

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor, Inc.
LIST OF TABLES
Table
Page
Number
Number
1-1 MC68F375 Pin Usage .......................................................................................... 1-8
2-1 Pin Characteristics................................................................................................. 2-1
2-2 Power Connections................................................................................................ 2-3
2-3 Output Driver Types............................................................................................... 2-4
2-4 Signal Characteristics ............................................................................................ 2-4
2-5 Signal Functions .................................................................................................... 2-6
3-1 Unimplemented MC68020 Instructions................................................................ 3-10
3-2 Instruction Set Summary ..................................................................................... 3-11
3-3 Exception Vector Assignments ............................................................................ 3-17
3-4 BDM Source Summary ........................................................................................ 3-21
3-5 Polling the BDM Entry Source ............................................................................. 3-22
3-6 Background Mode Command Summary.............................................................. 3-23
3-7 CPU Generated Message Encoding.................................................................... 3-26
4-1 SCIMMCR Bit Descriptions.................................................................................... 4-3
4-2 SCIMMCR Noise Control Bits................................................................................ 4-4
4-3 Show Cycle Enable Bits......................................................................................... 4-5
4-4 Effects of FREEZE Assertion................................................................................. 4-5
4-5 System Clock Sources........................................................................................... 4-6
4-6 CLKOUT Frequency: Slow Reference; 32.768 KHz Reference .......................... 4-10
4-7 CLKOUT In Fast Reference Mode with 4.0 MHz Reference ............................... 4-13
4-8 Port Reset Condition............................................................................................ 4-20
4-9 SYPCR Bit Descriptions ...................................................................................... 4-24
4-10 Bus Monitor Period ............................................................................................ 4-25
4-11 SWP Reset States ............................................................................................. 4-26
4-12 Software Watchdog Divide Ratio ....................................................................... 4-27
4-13 PTP Reset States .............................................................................................. 4-29
4-14 Periodic Interrupt Priority ................................................................................... 4-30
4-15 PICR Bit Descriptions ........................................................................................ 4-31
4-16 PITR Bit Descriptions......................................................................................... 4-31
4-17 Size Signal Encoding......................................................................................... 4-34
4-18 Address Space Encoding .................................................................................. 4-35
4-19 Effect of DSACK Signals ................................................................................... 4-36
4-20 Operand Alignment............................................................................................ 4-38
4-21 DSACK, BERR, and HALT Assertion Results ................................................... 4-47
4-22 Reset Source Summary..................................................................................... 4-55
4-23 RSR Bit Descriptions ......................................................................................... 4-56
4-24 SCIM2E Pin States During Reset ...................................................................... 4-59
4-25 Pins Associated with Basic Configuration Options ............................................ 4-60
4-26 Mode Configuration During Reset ..................................................................... 4-61
4-27 Fully (16-bit) Expanded Mode Reset Configuration........................................... 4-66
MC68F375
LIST OF TABLES
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
xxv
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