MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 478

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.8.4.2 BIUTBR — BIUSM Time Base Register
BIUTBR — BIUSM Time Base Register
13.9 Counter Prescaler Submodule (CPSM)
MC68F375
REFERENCE MANUAL
Bit(s)
MSB
10:8
15
7:6
5,0
4:1
0
RESET:
In normal operation, the BIUTBR is a read-only register used to read the value present
on one of the time base buses. The time base bus being accessed is determined by
TBRS1 and TBRS0 in the BIUMCR. Writing to the BIUTBR has no effect, except in
certain test modes.
The counter prescaler submodule (CPSM) generates six different clock frequencies
which can be used by any counter submodule. Five of these frequencies are derived
from a fixed divider. The divide ratio of the last clock frequency is software selectable
from a choice of four divide ratios. Note that this submodule is contained within the
BIUSM. A block diagram of the CPSM is given in
ratios available on PCLKx are also shown in the table in
Control
any or all CTM submodules.
14
0
IARG[2:0]
TBRS1,
TBRS0
Name
—
—
Register. These clock signals are provided on the SMB and may be used by
13
0
Interrupt arbitration identification. The interrupt arbitration bit field (IARB), composed of
IARB[2:0] in the BIUMCR and the IARB3 bit within each submodule, provides fifteen different
arbitration identification numbers that can be used to arbitrate between interrupt requests occur-
ring on the IMB with the same interrupt priority level.
The IARB field defaults to zero on reset, thus preventing the module from arbitrating during an
interrupt arbitration acknowledge cycle (IACK). If no IMB arbitration takes place during the IACK
cycle the spurious interrupt vector is generated by the SIM (system integration module). This
tells the system that the interrupt arbitration number has not been initialized. The seven levels
of interrupt are the primary means by which interrupt priority is established. The 4-bit interrupt
arbitration number is the secondary priority, allowing up to 15 requests at each primary level.
During the IACK cycle the request with the highest arbitration number gets serviced (binary 1111
is the highest priority and binary 0001 is the lowest).
Many IMB modules have one software assignable arbitration number for the whole module. The
CTM allows two different arbitration numbers to be used by providing each submodule with its
own IARB3 bit (which can be set or cleared in software). Once IARB[2:0] are assigned in the
BIUSM, they apply to all CTM interrupt requests. Therefore, CTM submodule interrupts can be
interleaved in priority with requests from other modules at the same interrupt level.
Reserved
Time base register bus select. These bits specify which time base bus is accessed when the
time base register (BIUTBR) is read.
00 = Time base bus TBB1
01 = Time base bus TBB2
10 = Time base bus TBB3
11 = Time base bus TBB4
Reserved
12
0
Table 13-19 BIUMCR Bit Settings (Continued)
MSB
Freescale Semiconductor, Inc.
11
0
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
10
0
Go to: www.freescale.com
9
0
Rev. 25 June 03
8
0
7
0
Description
6
0
Figure
5
0
13.9.2.1 CPCR — CPSM
13-14. The clock division
4
0
LSB
3
0
2
0
0xYF F204
MOTOROLA
1
0
13-52
LSB
0
0