MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 97

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

SYNCR — Synthesizer Control Register, External Clock Mode
4.3.6.1 Frequency control Bits (X,W,Y)
4.3.6.2 E Clock Divide Rate (EDIV)
4.3.6.3 Loss of Clock Oscillator Disable (LOSCD)
4.3.6.4 Limp Mode (SLIMP)
MC68F375
REFERENCE MANUAL
MSB
15
RESET:
X
1
Bits [15:8] of the SYNCR control the multiplication or division factors of the synthe-
sizer. X bit [15] controls a one-bit divider which drives the system clock in all modes.
When X is set, the divider is bypassed; when clear, the system clock is divided by two.
The W bits and the Y bits have different field lengths and functions depending on the
clock mode. In slow reference mode, bit [14] is the single W bit, and bits [13:8] are the
six Y bits, and both fields are used to multiply the reference frequency. In fast refer-
ence mode, bits [14:12] are the three W bits, which are used to multiply the reference
frequency. Bits [10:8] are the three Y bits, which are used to divide the PLL output fre-
quency. In external clock mode, bits [14:11] are unused, and bits [10:8] are the three
Y bits which are used to divide the input clock frequency. Refer to
4-7
The E clock that goes to the chip select section is driven from a divider circuit off of the
same clock source that drives the external clock. This allows turning off or leaving on
the E clock in LPSTOP mode using the STEXT bit. When EDIV=0, E is the system
clock divided by eight. When EDIV=1, E is the system clock divided by 16. EDIV is
cleared to zero by reset.
An internal oscillator is used in the detection of loss of clock. This oscillator can be dis-
abled by setting this bit. See
of this feature. When LOSCD = 1, the loss of clock oscillator is disabled. When LOSCD
= 0, the loss of clock oscillator is enabled. This bit is cleared to 0 on reset.
This read only status bit indicates whether the loss of crystal detect logic has detected
a loss of system clock. If a loss of clock is detected, the synthesizer will use an internal
RC oscillator to derive the system clock and enter limp mode, allowing the MCU to
continue to run even without an external clock.
SLIMP=0 indicates that the system clock is being provided normally, either by the PLL
or by an external clock from the EXTAL input. SLIMP=1 indicates that a loss of system
clock has been detected, and the system clock is being provided from the loss of crys-
tal oscillator reference. See
clock is approximately 16 KHz.
14
0
for system frequencies available in common configurations.
Reserved
13
0
12
0
11
0
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
10
0
For More Information On This Product,
Y
9
0
8
0
4.3.7.5 Loss Of Clock Detect Circuit
4.3.7.5 Loss Of Clock Detect Circuit (LOC)
Go to: www.freescale.com
EDIV
7
0
Rev. 25 June 03
served
Re-
6
0
LOSCD
5
0
SLIMP
4
0
SLOCK
3
1
Table 4-6
RSTEN
2
0
(LOC). The limp
STSCIM
0xYF FA04
1
0
MOTOROLA
and
for details
STEXT
Table
LSB
0
0
4-15