MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 190

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.9.2 Front-End Analog Multiplexer
5.9.3 Digital-to-Analog Converter Array
5.9.4 Comparator
5.9.5 Successive Approximation Register
5.10 Digital Control Subsystem
MC68F375
REFERENCE MANUAL
The internal multiplexer selects one of the 16 analog input pins or one of three special
internal reference channels for conversion. The following are the three special
channels:
The selected input is connected to one side of the DAC capacitor array. The other side
of the DAC array is connected to the comparator input. The multiplexer also includes
positive and negative stress protection circuitry, which prevents other channels from
affecting the present conversion when excessive voltage levels are applied to the
other channels. Refer to
cific voltage level limits.
The digital-to-analog converter (DAC) array consists of binary-weighted capacitors
and a resistor-divider chain. The array serves two purposes:
Resolution begins with the MSB and works down to the LSB. The switching sequence
is controlled by the SAR logic.
The comparator is used during the approximation process to sense whether the digi-
tally selected arrangement of the DAC array produces a voltage level higher or lower
than the sampled input. The comparator output feeds into the SAR which accumulates
the A/D conversion result sequentially, starting with the MSB.
The input of the successive approximation register (SAR) is connected to the compar-
ator output. The SAR sequentially receives the conversion value one bit at a time,
starting with the MSB. After accumulating the ten bits of the conversion result, the SAR
data is transferred by the queue control logic in the digital section to the appropriate
result location, where it may be read by user software.
The digital control subsystem includes the clock and periodic/interval timer, control
and status registers, the conversion command word table RAM, and the result word
table RAM.
The central element for control of QADC64 conversions is the 64-entry conversion
command word (CCW) table. Each CCW specifies the conversion of one input chan-
nel. Depending on the application, one or two queues can be established in the CCW
• V
• V
• (V
• The array holds the sampled input voltage during conversion.
• The resistor-capacitor array provides the mechanism for the successive approx-
imation A/D conversion.
RH
RL
RH
— Reference voltage low
— Reference voltage high
– V
RL
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
)/2 — Mid-reference voltage
Freescale Semiconductor, Inc.
For More Information On This Product,
APPENDIX E ELECTRICAL CHARACTERISTICS
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
for spe-
5-14