MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 419

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

12.4.2 ROM Base Address Register (ROMBAH, ROMBAL)
ROMBAH — ROM Base Address High Register
ROMBAL — ROM Base Address Low Register
MC68F375
REFERENCE MANUAL
Bit(s)
MSB
MSB
NOTES:
NOTES:
31
15
U
9:8
7:6
5:0
0
RESET:
RESET:
2
The default reset ROM base address fields are specified by the user along with the
contents of the array and are programmed on the same mask layer as the contents of
the array.
1. Indicates bits protected by LOCK and STOP. The default state of these bits is defined by customer-specified
2. The default state of these bits is defined by customer specified options.
1. Indicates bits protected by LOCK and STOP. The default state of these bits is defined by customer-specified
options.
options.
U
30
14
ROMBAL
0
ASPC[1:0]
WAIT[1:0]
2
Name
—
29
13
U
0
1
2
ROM array space. The ASPC[1:0] field is forced to the default reset state by master reset. The
default reset state of the ASPC[1:0] field is specified by the user at mask programming time and
is programmed on the same mask layer as the contents of the array. IFC[2:0] is checked by the
ROM module BIU to determine if a user or supervisor is requesting array access. If a supervisor
program is accessing the array, normal read operation will occur. If a user program is attempting
to access the array, the access will be ignored and the address may be decoded externally.
00 = Unrestricted program and data space IFC[2:0] = x01, x10.
01 = Unrestricted program space only. IFC[2:0] = x10.
10 = Supervisor data and program space only. IFC[2:0] = 101, 110.
11 = Supervisor program space only. IFC[2:0] = 110.
Wait states. The WAIT field is used to specify the number of WAIT states inserted by the ROM
BIU during accesses to the ROM module before asserting IDTACKB. A WAIT state has a dura-
tion of one system clock cycle. This affects both control block access and array access. This
feature allows the migration of storage space from a slower emulation or development system
memory to the onboard ROM module without the need for retiming the system. The default reset
state of the WAIT field is specified by the user at mask programming time and is programmed
on the same mask layer as the contents of the array. The WAIT field may be written any time
the LOCK bit is 0.
00 = 3 clocks per transfer.
01 = 4 clocks per transfer
10 = 5 clocks per transfer
11 = 2 clocks per transfer
Reserved
RESERVED
28
12
U
0
Table 12-2 ROMMCR Bit Settings (Continued)
2
Freescale Semiconductor, Inc.
27
11
0
0
For More Information On This Product,
26
10
0
0
Go to: www.freescale.com
MASK ROM MODULE
25
0
9
0
Rev. 25 June 03
24
0
8
0
U
23
7
0
2
Description
RESERVED
22
U
6
0
2
21
U
5
0
2
ROMBAH
U
20
4
0
2
19
U
3
0
1
2
18
U
2
0
2
0xYF F824
0xYF F826
MOTOROLA
U
17
1
0
2
LSB
LSB
12-5
U
16
0
0
2