MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 560

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

D.17.3.1 XFER_SIZE Greater than 16
D.17.3.2 Data Positioning
D.17.3.3 Data Timing
MC68F375
REFERENCE MANUAL
S1 SIOP_INIT
HSQ = X0
X1
S2 DATA_OUT
HSQ = X0
X1
S3 DATA_IN
HSQ = 0X
1X
NOTES:
1. Execution times do not include the time slot transition time (TST = 10 or 14 CPU clocks).
XFER_SIZE is normally programmed to be in the range 1-to-16 to match the size of
SIOP_DATA, and has thus been shown as a 5-bit value in the host interface diagram.
However, the TPU actually uses all 16 bits of the XFER_SIZE parameter when loading
BIT_COUNT. In some unusual circumstances this can be used to the user’s advan-
tage. If an input device is producing a data stream of greater than 16 bits then manip-
ulation of XFER_SIZE will allow selective capturing of the data. In clock-only mode,
the extended XFER_SIZE can be used to generate up to $FFFF clocks.
As stated above, no ‘justifying’ of the data position in SIOP_DATA is performed by the
TPU. This means that in the case of a byte transfer, the data output will be sourced
from one byte and the data input will shift into the other byte. This rule holds for all
data size options except 16 bits when the full SIOP_DATA register is used for both
data output and input.
In the example given in
completely synchronous with the relevant clock edge and it is assumed that the data
input is latched exactly on the opposite clock edge. This is the simplest way to show
the examples, but is not strictly true. Since the TPU is a multi-tasking system, and the
data channels are manipulated directly by microcode software while servicing the
clock edge, there is a finite delay between the relevant clock edge and the data-out
being valid or the data-in being latched. This delay is equivalent to the latency in ser-
vicing the clock channel due to other TPU activity and is shown as ‘Td’ in the timing
diagram. Td is the delay between the clock edge and the next output data being valid
and also the delay between the opposite clock edge and the input data being read. For
the vast majority of applications, the delay Td will not present a problem and can be
ignored. Only for a system which heavily loads the TPU should the user calculate the
worst case latency for the SIOP clock channel + actual SIOP service time ( = Td) and
ensure that the baud rate is chosen such that HALF_PERIOD - Td is not less that the
State Number and Name
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure
Table D-4 SIOP State Timing
Go to: www.freescale.com
TPU ROM FUNCTIONS
D-29, the data output transitions are shown as being
Max. CPU Clock Cycles
Rev. 25 June 03
28
38
14
24
14
28
1
Number of RAM Accesses by TPU
7
7
4
4
4
6
MOTOROLA
D-46