MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 258

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.4 QSPI Operation
MC68F375
REFERENCE MANUAL
Master in slave out
Master out slave in
Serial clock
Peripheral chip selects
Peripheral chip select
Slave select
Slave select
NOTES:
The QSPI uses a dedicated 160-byte block of static RAM accessible by both the QSPI
and the CPU to perform queued operations. The RAM is divided into three segments:
32 command control bytes, 64 transmit data bytes, and 64 receive data bytes.
Once the CPU has set up a queue of QSPI commands, written the transmit data seg-
ment with information to be sent, and enabled the QSPI, the QSPI operates
independently of the CPU. The QSPI executes all of the commands in its queue, sets
a flag indicating completion, and then either interrupts the CPU or waits for CPU
intervention.
QSPI RAM is organized so that one byte of command data, one word of transmit data,
and one word of receive data correspond to each queue entry, 0x0 to 0x2F.
The CPU initiates QSPI operation by setting up a queue of QSPI commands in com-
mand RAM, writing transmit data into transmit RAM, then enabling the QSPI. The
QSPI executes the queued commands, sets a completion flag (SPIF), and then either
interrupts the CPU or waits for intervention.
There are four queue pointers. The CPU can access three of them through fields in
QSPI registers. The new queue pointer (NEWQP), contained in SPCR2, points to the
first command in the queue. An internal queue pointer points to the command currently
being executed. The completed queue pointer (CPTQP), contained in SPSR, points to
the last command executed. The end queue pointer (ENDQP), contained in SPCR2,
points to the final command in the queue.
The internal pointer is initialized to the same value as NEWQP. During normal opera-
tion, the command pointed to by the internal pointer is executed, the value in the
internal pointer is copied into CPTQP, the internal pointer is incremented, and then the
1. All QSPI pins (except SCK) can be used as general-purpose I/O if they are not used by the QSPI while the QSPI
2. An output (PCS0) when the QSPI is in master mode.
3. An input (SS) when the QSPI is in slave mode.
4. An input (SS) when the QSPI is in master mode; useful in multimaster systems.
is operating. SCK can only be used for general-purpose I/O if the QSPI is disabled.
Pin Names
3
4
2
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Mnemonic
PCS[1:3]
Table 6-20 QSPI Pin Functions
PCS0/
MISO
MOSI
SCK
SS
SS
1
Go to: www.freescale.com
Rev. 25 June 03
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Serial data input to QSPI
Serial data output from QSPI
Serial data output from QSPI
Serial data input to QSPI
Clock output from QSPI clock
Input to QSPI
Outputs select peripheral(s)
Output selects peripheral(s)
Input selects the QSPI
May cause mode fault
Function
MOTOROLA
6-24