MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 165

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
If the chip select is configured to trigger on an interrupt acknowledge cycle
(SPACE[1:0] = 0b00) and the AVEC field is set to one, the chip select automatically
generates AVEC and completes the interrupt acknowledge cycle. If the AVEC bit = 0,
then the vector must be supplied by the requesting external device to complete the
IACK read cycle.
The BYTE field controls the data placement conditions under which a particular chip
select asserts. This is a different function from that of the chip-select pin assignment
registers which determine if transfers controlled by a particular chip select are funda-
mentally eight or sixteen bits in length. Instead, BYTE[1:0] specifies whether the chip
select will assert for data placed on the lower half, upper half, or both halves of the data
bus.
When a chip select is configured for 8-bit port operation, only DATA[15:8] are used.
Consequently, any BYTE field value other than 0b00 will permit signal assertion when
all other match conditions are met.
When a chip select is configured for 16-bit port operation, BYTE[1:0] determines which
combinations of ADDR0 and SIZ0 will result in chip-select assertion. A chip select con-
figured for both bytes (0b11) will assert (assuming all other conditions are met)
regardless of the states of ADDR0 and SIZ0. A chip select configured for upper byte
(0b10) will assert only when ADDR0 = 0 (even addresses). A chip select configured
for lower byte (0b01) must assert on all accesses to odd addresses (ADDR0 = 1) and
on word accesses to even addresses (ADDR0 = 0 and SIZ0 = 1). When the boolean
expression ADDR0
cases, the routing of information onto the data bus by the EBI data multiplexer is con-
trolled by ADDR0 and SIZ0.
When SPACE[1:0] = 0b00 (CPU space), IPL[2:0] specifies the interrupt priority that
must be matched when chip-select logic is used to terminate IACK cycles generated
in response to external requests for interrupt service. When SPACE[1:0] is set to 0b00
(CPU space), ADDR[3:1] is compared to the IPL field at the beginning of an IACK
cycle. If these values are the same (and other option register constraints are satisfied),
NOTES:
Table 4-39 Interrupt Priority Level Field Encoding
IPL[2:0]
1. Any level means that chip select is asserted regardless of the level of the
interrupt acknowledge cycle.
000
001
010
011
100
101
110
111
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
·
SIZ0 is false, lower byte chip-select assertion will occur. In all
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
Interrupt Priority Level
Any Level
1
2
3
4
5
6
7
1
MOTOROLA
4-83