MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 217

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
12:8
6:0
15
14
13
7
RESUME
Name
SSE2
CIE2
PIE2
MQ2
BQ2
Queue 2 completion interrupt enable. CIE2 enables completion interrupts for queue 2. The inter-
rupt request is generated when the conversion is complete for the last CCW in queue 2.
0 = Queue 2 completion interrupts disabled.
1 = Generate an interrupt request after completing the last CCW in queue 2.
request is generated when the conversion is complete for a CCW that has the pause bit set.
0 = Queue 2 pause interrupts disabled.
1 = Generate an interrupt request after completing a CCW in queue 2 which has the pause bit set.
occurs. The SSE2 bit may be set to a one during the same write cycle that sets the MQ2 bits for
the single-scan queue operating mode. The single-scan enable bit can be written as a one or a
zero, but is always read as a zero.
The SSE2 bit allows a trigger event to initiate queue execution for any single-scan operation on
queue 2. The QADC64 clears SSE2 when the single-scan is complete.
5-15
1. If RESUME is changed during execution of queue 2, the change is not recognized until an end-
of-queue condition is reached, or the queue operating mode of queue 2 is changed.
0 = After suspension, begin execution with the first CCW in queue 2 or the current subqueue.
1 = After suspension, begin execution with the aborted CCW in queue 2.
begins. The BQ2 field also indicates the end-of-queue 1 and thus creates an end-of-queue con-
dition for queue 1. Setting BQ2 to any value
queue 1 CCW’s.
Queue 2 operating mode. The MQ2 field selects the queue operating mode for queue 2.
Queue 2 resume. RESUME selects the resumption point after queue 2 is suspended by queue
Queue 2 pause interrupt enable. PIE2 enables pause interrupts for queue 2. The interrupt
Queue 2 single-scan enable bit. SSE2 enables a single-scan of queue 2 after a trigger event
Beginning of queue 2. The BQ2 field indicates the location in the CCW table where queue 2
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
shows the bits in the MQ2 field which enable different queue 2 operating modes.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5-14 QACR2 Bit Settings
Go to: www.freescale.com
Rev. 25 June 03
Description
64 (1000000) allows the entire RAM space for
MOTOROLA
Table
5-41