MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 387

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

CMFICTL2 — CMFI High Voltage Control Register 2
MC68F375
REFERENCE MANUAL
Bit(s)
MSB
Bit(s)
15:8
15
6:0
7:6
0
RESET:
7
5
4
3
14
0
CLKPM
BLOCK
PEEM
Name
Name
B0EM
—
—
—
13
0
Reserved
Clock period multiple select. The CLKPM[6:0] bits are write protected by the SES bit. Writes to
CMFICTL will not change CLKPM[6:0] if SES = 1. The third term of the timing control is the linear
clock multiplier, M. The clock period multiplier, CLKPM[6:0], defines a linear multiplier for the
program or erase pulse. The multiplier, M, is defined by the equation:
This allows for the program/erase pulse to be from 1 to 128 times the pulse set by the system
clock period, SCLKR[2:0] and CLKPE[1:0].
Block program and erase select. The BLOCK[7:0] bits are write protected by the SES bit. Writes
to CMFICTL will not change BLOCK[7:0] if SES = 1. BLOCK[7:0] selects the CMFI EEPROM
array blocks for program and erase operation. Up to eight blocks may be selected for program
or erase operation at once. The CMFI EEPROM configuration along with BLOCK[7:0] determine
the blocks that will be programmed simultaneously. The CMFI EEPROM array blocks that are
selected to be programmed by the program operation are the blocks where BLOCK[M] = 1. The
CMFI EEPROM configuration along with BLOCK[7:0] determine the blocks that will be erased
simultaneously. The CMFI EEPROM array blocks that are selected to be erased by the erase
operation are the blocks where BLOCK[M] = 1.
The block bit must be set only for the blocks currently being programed. If the block bits are set
for blocks that are not being programmed, the contents of the other blocks could be disturbed.
0 = Array block M is not selected for program or erase.
1 = Array block M is selected for program or erase.
Reserved
Program erase enable monitor. The CMFI will sample the E
MC68F375) when EHV is asserted and hold the E
nal has a digital filter that requires two consecutive samples to be equal before the output of the
filter will change.
0 = High voltage operations are not possible.
1 = High voltage operations are possible.
Block zero enable monitor. The CMFI will sample B0EM when EHV is asserted and hold the
B0EM state until EHV is negated. The optional E
signal. If B0EM = 1 when EHV is asserted, high voltage operations to CMFI array block 0 such
as program or erase are enabled. While, if B0EM = 0 when EHV is asserted high voltage oper-
ations to CMFI array block 0 are disabled.
0 = High voltage operations in Array Block 0 are not possible.
1 = High voltage operations in Array Block 0 are possible.
Reserved
12
0
Table 10-9 CMFICTL1 Bit Settings (Continued)
BLOCK
Freescale Semiconductor, Inc.
11
0
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Table 10-10 CMFICTL2 Bit Settings
M = 1 + CLKPM[6:0]
10
0
Go to: www.freescale.com
9
0
Rev. 25 June 03
8
0
7
0
0
Description
Description
WARNING
6
0
0
PEB0
PEE
PEEM
5
0
state until EHV is negated. The E
pin has a digital filter similar to the E
B0EM
PEE
4
0
signal (always enabled on the
3
0
0
PE
2
0
0xYF F80E
MOTOROLA
SES
1
0
PEE
10-17
EHV
LSB
PEE
0
0
sig-