MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 278

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.8.1 SCI Registers
MC68F375
REFERENCE MANUAL
The SCI programming model includes the QSMCM global and pin control registers
and the DSCI registers.
The DSCI registers, listed in
registers, and 34 data registers. All registers may be read or written at any time by the
CPU. Rewriting the same value to any DSCI register does not disrupt operation; how-
ever, writing a different value into a DSCI register when the DSCI is running may
disrupt operation. To change register values, the receiver and transmitter should be
disabled with the transmitter allowed to finish first. The status flags in register SCxSR
During SCIx initialization, two bits in the SCCxR1 should be written last: the transmitter
enable (TE) and receiver enable (RE) bits, which enable SCIx. Registers SCCxR0 and
SCCxR1 should both be initialized at the same time or before TE and RE are asserted.
can be cleared at any time.
(non-queue mode only)
*Reads access the RDRx; writes access the TDRx.
0xYF FC2C —
0xYF FC4C —
00xYF FC0E
0xYF FC0C
0xYF FC0A
0xYF FC2A
0xYF FC4A
0xYF FC6A
0xYF FC08
0xYF FC20
0xYF FC22
0xYF FC24
0xYF FC26
0xYF FC28
Address
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
QSCI1 Transmit Queue
QSCI1 Receive Queue
Table 6-22 SCI Registers
Table
Memory Area
Memory Area
Go to: www.freescale.com
QSCI1CR
QSCI1SR
SCC1R0
SCC1R1
SCC2R0
SCC2R1
SC1DR
SC2DR
SC1SR
SC2SR
Name
Rev. 25 June 03
6-22, consist of five control registers, three status
SCI1 Control Register 0
See
SCI1 Control Register 1
See
SCI1 Status Register
See
SCI1 Data Register
Transmit Data Register (TDR1)*
Receive Data Register (RDR1)*
See
SCI2 Control Register 0
SCI2 Control Register 1
SCI2 Status Register
SCI2 Data Register
Transmit Data Register (TDR2)*
Receive Data Register (RDR2)*
QSCI1 Control Register
Interrupts, wrap, queue size and enables
for receive and transmit, QTPNT.
See
QSCI1 Status Register
OverRun error flag, queue status flags,
QRPNT, and QPEND.
See
QSCI1 Transmit Queue Data locations (on
half-word boundary)
QSCI1 Receive Queue Data locations (on
half-word boundary)
Table 6-23
Table 6-24
Table 6-25
Table 6-26
Table 6-31
Table 6-32
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
Usage
MOTOROLA
6-44