MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 254

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.1.5 QSPI Status Register
SPSR — QSPI Status Register
MC68F375
REFERENCE MANUAL
Bit(s)
15:11
MSB
15
7:0
10
9
8
The SPSR contains information concerning the current serial transmission. Only the
QSPI can set bits in this register. To clear status flags, the CPU reads SPSR with the
flags set and then writes the SPSR with zeros in the appropriate bits. Writes to CPTQP
have no effect.
*See bit descriptions in
14
LOOPQ
Name
HMIE
HALT
—
—
13
SPSR.
Reserved
QSPI loop mode. LOOPQ controls feedback on the data serializer for testing.
0 = Feedback path disabled.
1 = Feedback path enabled.
HALTA and MODF interrupt enable. HMIE enables interrupt requests generated by the HALTA
status flag or the MODF status flag in SPSR.
0 = HALTA and MODF interrupts disabled.
1 = HALTA and MODF interrupts enabled.
from which it can later be restarted. Refer to
0 = QSPI operates normally.
1 = QSPI is halted for subsequent restart.
Halt QSPI. When HALT is set, the QSPI stops on a queue boundary. It remains in a defined state
12
SPCR3*
Table
SeeTable 6-18
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
11
For More Information On This Product,
6-17.
Table 6-17 SPCR3 Bit Settings
10
Go to: www.freescale.com
for bit descriptions.
9
Rev. 25 June 03
8
SPIF
7
0
Description
6.7.4.1 Enabling, Disabling, and Halting the
MODF
6
0
HAL-
TA
5
0
4
0
3
0
CPTQP
2
0
0xYF FC1F
MOTOROLA
1
0
LSB
6-20
SPI.
0
0