MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 432

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.2.2 FCSM Clock Sources
13.2.3 FCSM External Event Counting
13.2.4 The FCSM Time Base Bus Driver
13.2.5 FCSM Interrupts
13.2.6 Freeze Action on the FCSM
MC68F375
REFERENCE MANUAL
The user can choose from eight software selectable counter clock sources:
The clock source is selected by the CLK[2:0] bits in the FCSM status, interrupt and
control register FCSMSIC (see
trol
that spurious edges occurring on the CTMC pin do not affect the FCSM.
Note that the read-only IN bit of the FCSMSIC register reflects the state of the input
pin CTMC. The input pin is Schmitt triggered and is synchronized with the system
clock (f
When an external clock source (on the input pin) is selected, the FCSM is in the event
counter mode. The counter can simply count the number of events occurring on the
input pin. Alternatively, the FCSM can be programmed to generate an interrupt when
a predefined number of events have been counted; this is done by presetting the
counter with the two’s complement value of the desired number of events. When using
the external clock source, the maximum guaranteed external frequency is f
The DRVA and DRVB bits in the FCSMSIC register select the time base buses to be
driven (see
A valid FCSM interrupt can be generated when the COF bit in the FCSMSIC register
is set (as a result of the counter overflowing). If the interrupt priority level of the FCSM
is non-zero, as defined by the three IL bits in the FCSMSIC register, a valid interrupt
request will occur on the IMB.
When the IMB FREEZE signal is recognized, the FCSM counter stops counting and
remains set at its current value. When the FREEZE signal is negated, the counter
starts incrementing from its current value, as if nothing had happened. All registers are
accessible during freeze.
• Six prescaler outputs (PCLKx)
• Input pin rising edge detection on the input pin CTMC
• Input pin falling edge detection on the input pin CTMC
Register). When the CLK[2:0] bits are being changed, internal circuitry ensures
SYS
COF flag and does not generate an interrupt request.
It is not recommended that the two time base buses be driven at the
same time.
).
13.2.7.1 FCSMSIC — FCSM Status/Interrupt/Control
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Go to: www.freescale.com
13.2.7.1 FCSMSIC — FCSM Status/Interrupt/Con-
Rev. 25 June 03
WARNING
Register).
MOTOROLA
SYS
/4.
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