MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 558

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

D.17.1.1 CHAN_CONTROL
D.17.1.2 BIT_D
D.17.1.3 HALF_PERIOD
D.17.1.4 BIT_COUNT
D.17.1.5 XFER_SIZE
D.17.1.6 SIOP_DATA
MC68F375
REFERENCE MANUAL
NOTES:
This 9-bit CPU written parameter is used to setup the clock polarity for the SIOP data
transfer. The valid values for CHAN_CONTROL for this function are given in the table
below. CHAN_CONTROL must be written by the host prior to issuing the host service
request (HSR) to initialize the function.
1. Other values of CHAN_CONTROL may result in indeterminate operation.
BIT_D is a CPU written bit that determines the direction of shift of the SIOP data. If
BIT_D is zero then SIOP_DATA is right shifted (lsb first). If BIT_D is one then
SIOP_DATA is left shifted (msb first).
This CPU-written parameter defines the baud rate of the SIOP function. The value
contained in HALF_PERIOD is the number of TCR1 counts for a half SIOP clock pe-
riod (e.g., for a 50 KHz baud rate, with a TCR1 period of 240 ns, the value [(1/50 KHz)/
2]/240 ns = 42 should be written to HALF_PERIOD. The range for HALF_PERIOD is
1 to $8000, although the minimum value in practice will be limited by other system con-
ditions. See notes on use and performance of SIOP function.
This parameter is used by the TPU to count down the number bits remaining while a
transfer is in progress. During the SIOP initialization state, BIT_COUNT is loaded with
the value contained in XFER_SIZE. It is then decremented as the data is transferred
and when it reaches zero, the transfer is complete and the TPU issues an interrupt re-
quest to the CPU.
This CPU-written parameter determines the number of bits that make up a data trans-
fer. During initialization, XFER_SIZE is copied into BIT_COUNT. XFER_SIZE is
shown as a 5-bit parameter to match the maximum size of 16 bits in SIOP_DATA, al-
though the TPU uses the whole word location. For normal use, XFER_SIZE should
be in the range 1-to-16.
This parameter is the data register for all SIOP transfers. Data is shifted out of one
end of SIOP_DATA and shifted in at the other end, the shift direction being determined
by the value of BIT_D. In output only mode, zero will be shifted into SIOP_DATA and
CHAN_CONTROL
8 7 6 5 4 3 2 1 0
0 1 0 0 0 1 1 0 1
0 1 0 0 0 1 1 1 0
Table D-3 SIOP Function Valid CHAN_Control Options
Freescale Semiconductor, Inc.
1
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TPU ROM FUNCTIONS
Data valid on clock Falling edge.
Data valid on clock Rising edge.
Rev. 25 June 03
Resulting Action
MOTOROLA
D-44