MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 210

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
The QADC64 has two global registers for configuring module operation: the module
configuration register (QADC64MCR) and the interrupt register (QADC64INT). The
global registers are always defined to be in supervisor data space. The CPU allows
software to establish the global registers in supervisor data space and the remaining
registers and tables in user space.
NOTES:
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
1. S = Supervisor only
2. Access is restricted to supervisor only and factory test mode only.
3. S/U = Unrestricted or supervisor depending on the state of the SUPV bit in the QADC64MCR.
S
T
—
S
2
1
3
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
0xYF F600 — 0xYF F67F
0xYF F414 – 0xYF F5FE
0xYF F680 – 0xYF F6FE
0xYF F700 – 0xYF F77E
0xYF F780 – 0xYF F7FE
Freescale Semiconductor, Inc.
For More Information On This Product,
0xYF F40A
0xYF F40C
0xYF F40E
0xYF F400
0xYF F402
0xYF F404
0xYF F406
0xYF F408
0xYF F410
0xYF F412
Address
Table 5-6 QADC64 Address Map
Go to: www.freescale.com
Rev. 25 June 03
MSB
Port A Data (PORTQA)
See
Left-Justified, Signed Result Register (LJSRR)
Conversion Command Word (CCW) Table
Right-Justified, Unsigned Result Register
Port A Data Direction Register (DDRQA)
QADC64 Module Configuration Register
QADC64 Test Register (QADC64TEST)
Left-Justified, Unsigned Result Register
See
See
See
Table 5-10
descriptions.
QADC64 Control Register 0 (QACR0)
QADC64 Control Register 1 (QACR1)
QADC64 Control Register 2 (QACR2)
QADC64 Status Register 0 (QASR0)
QADC64 Status Register 1 (QASR1)
See
See
See
See
See
See
See
See
See
Interrupt Register (QADC64INT)
5.12.11 Result Word Table
5.12.11 Result Word Table
5.12.11 Result Word Table
Table 5-10
Table 5-11
Table 5-12
Table 5-14
Table 5-16
Table 5-16
Table 5-19
Table 5-7
Table 5-8
Result Word Table
Result Word Table
Result Word Table
(QADC64MCR)
for bit
descriptions.
descriptions.
descriptions.
Reserved
(RJURR)
(LJURR)
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
Port B Data (PORTQB)
for bit
for bit
for bit
LSB
MOTOROLA
5-34