MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 22

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

Number
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8-1
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MC68F375
REFERENCE MANUAL
Figure
QADC64 Block Diagram ................................................................................. 5-1
QADC64 Input and Output Signals ................................................................. 5-3
Example of Full External Multiplexing ........................................................... 5-10
QADC64 Module Block Diagram .................................................................. 5-12
Conversion Timing ........................................................................................ 5-13
Bypass Mode Conversion Timing ................................................................. 5-13
QADC64 Queue Operation with Pause ........................................................ 5-16
QADC64 Clock Subsystem Functions .......................................................... 5-26
QADC64 Clock Programmability Examples ................................................. 5-28
QADC64 Interrupt Flow Diagram .................................................................. 5-30
QADC64 Interrupt Vector Format ................................................................. 5-33
QADC64 Conversion Queue Operation ....................................................... 5-46
AMUX/QADC64 Configured for Mixed Multiplexing ..................................... 5-55
Analog Multiplexer Submodule Charging Current Illustration ....................... 5-57
QSMCM Block Diagram ................................................................................. 6-2
QSPI Block Diagram ..................................................................................... 6-14
QSPI RAM .................................................................................................... 6-22
Flowchart of QSPI Initialization Operation .................................................... 6-27
Flowchart of QSPI Master Operation (Part 1) ............................................... 6-28
Flowchart of QSPI Master Operation (Part 2) ............................................... 6-29
Flowchart of QSPI Master Operation (Part 3) ............................................... 6-30
Flowchart of QSPI Slave Operation (Part 1) ................................................. 6-31
Flowchart of QSPI Slave Operation (Part 2) ................................................. 6-32
SCI Transmitter Block Diagram .................................................................... 6-42
SCI Receiver Block Diagram ........................................................................ 6-43
Queue Transmitter Block Enhancements ..................................................... 6-60
Queue Transmit Flow ................................................................................... 6-62
Queue Transmit Software Flow .................................................................... 6-63
Queue Transmit Example for 17 Data Bytes ................................................ 6-64
Queue Transmit Example for 25 Data Frames ............................................. 6-65
Queue Receiver Block Enhancements ......................................................... 6-66
Queue Receive Flow .................................................................................... 6-69
Queue Receive Software Flow ..................................................................... 6-70
Queue Receive Example for 17 Data Bytes ................................................. 6-71
TouCAN Block Diagram ................................................................................. 7-1
Typical CAN Network ..................................................................................... 7-3
Extended ID Message Buffer Structure .......................................................... 7-4
Standard ID Message Buffer Structure ........................................................... 7-4
TouCAN Interrupt Vector Generation ........................................................... 7-19
TouCAN Message Buffer Memory Map ........................................................ 7-23
TPU3 Block Diagram ...................................................................................... 8-1
TCR1 Prescaler Control ................................................................................. 8-7
TCR2 Prescaler Control ................................................................................. 8-8
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
LIST OF FIGURES
Rev. 25 June 03
MOTOROLA
Number
Page
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