MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 174

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.10.4.2 Port F Data Direction Register
DDRF — Port F Data Direction Register
4.10.4.3 Port F Pin Assignment Register
PFPAR — Port F Pin Assignment Register
MC68F375
REFERENCE MANUAL
RESET:
RESET
DATA9
This register controls the direction of the port F pin drivers when pins are configured
for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit
configures the corresponding pin as an input. This register can be read or written at
any time. Bits [15:8] are reserved and will always read zero.
This register determines the function of port F pins. Setting a bit assigns the corre-
sponding pin to a control signal; clearing a bit assigns the pin to port F. Bits [15:8] are
reserved and will always read zero.
4-45
DDF7
MSB
MSB
7
0
7
0
shows PFPAR pin functions.
PFPA3
DATA9
DDF6
6
0
6
0
PFPAR Field
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
PFPA3
PFPA2
PFPA1
PFPA0
PFPAx[1:0]
DATA9
For More Information On This Product,
Table 4-44 Port F Pin Assignments
DDF5
Table 4-45 PFPAR Pin Functions
5
0
5
0
00
01
10
11
PFPA2
8- AND 16-BIT EXPANDED MODES
Go to: www.freescale.com
DATA9
DDF4
Port F Signal
SINGLE-CHIP MODE
Rev. 25 June 03
4
0
4
0
PF[7:6]
PF[5:4]
PF[3:2]
PF[1:0]
Table 4-44
I/O pin without edge detect
DATA9
Falling edge detect
DDF3
Rising edge detect
Interrupt request
3
0
3
0
Port F Signal
shows port F pin assignments.
PFPA1
Alternate Signal
IRQ1, FASTREF
IRQ[7:6]
IRQ[5:4]
IRQ[3:2]
DATA9
DDF2
2
0
2
0
DATA9
DDF1
1
0
1
0
PFPA0
0xYF FA1D
0xYF FA1F
MOTOROLA
DATA9
DDF0
LSB
LSB
0
0
0
0
Table
4-92