MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 609

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

QASR0 5-43
QASR1 5-44
QCLK 5-24
QDDR 6-12, 6-41
QOM D-5
QPAR 6-10
QPDR 6-10, 6-41
QS 5-44
QSM
QSM Data Direction Register (QDDR) 6-12, 6-41
QSM Pin Assignment Register (QPAR) 6-10
QSM Port Data Register (QPDR) 6-10, 6-41
QSPI 6-13
QSPI Enable (SPE) 6-41
QSPI Status Register (SPSR) 6-41
MC68F375
REFERENCE MANUAL
frequency 5-25
pin function 6-10
QSPI 6-13
registers
SCI 6-41
block diagram 6-14
enable (SPE) 6-18
finished flag (SPIF) 6-21
initialization operation 6-27
loop mode (LOOPQ) 6-20
master operation flow 6-28
operating modes 6-26
operation 6-24
peripheral chip-selects 6-36
RAM 6-21, 6-22
timing
operating modes 6-26
operation 6-24
RAM 6-21
pin control registers 6-8
QSPI
SCI
operation 6-50
pins 6-50
registers 6-44
master mode 6-26, 6-33
slave mode 6-26, 6-37
command RAM 6-22
receive RAM 6-22
transmit RAM 6-22
master E-21
slave E-22
port QS
control register 0 (SPCR0) 6-16
control register 1 (SPCR1) 6-18
control register 2 (SPCR2) 6-18
control register 3 (SPCR3) 6-19
status register (SPSR) 6-19
control register 0 (SCCR0) 6-45
control register 1 (SCCR1) 6-45
data register (SCDR) 6-49
status register (SCSR) 6-47
wraparound mode 6-37
data direction register (DDRQS) 6-9
data register (PORTQS) 6-9
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
INDEX
Quad-word data 3-4
Queue 5-15
Queue 1
Queue 2
Queued
Queued output match TPU function (QOM) D-5
R/W 4-4, 4-5, 4-34, 4-39, 4-42, 4-62, 4-66
RAF 6-48
RAMBAH, RAMBAL 11-5
RASP
RC
RDRF 6-48, 6-55
RE 6-44, 6-46, 6-54
Read
Receive
Receiver
pointers
status (QS) 5-44
completion
operating mode (MQ1) 5-39
pause
single-scan enable (SSE1) 5-39
trigger overrun (TOR1) 5-43
completion
operating mode (MQ2) 5-41
pause
resume (RES) 5-41
single-scan enable bit (SSE2) 5-41
trigger overrun (TOR2) 5-43
analog-to-digital converter. See QADC 5-1
serial
parameters D-6
field 4-81
encoding 11-4
oscillator 4-22
/write signal (R/W). See R/W 4-34
cycle 4-40
system register command (RSREG) 3-22
data
error status flag (RXWARN) 7-32
RAM 6-22
time sample clock (RT) 6-51, 6-54
active (RAF) 6-48
completed queue pointer (CPTQP) 6-24
end queue pointer (ENDQP) 6-24
new queue pointer (NEWQP) 6-24
flag (CF1) 5-43
interrupt enable (CIE1) 5-39
flag (PF1) 5-43
interrupt enable (PIE1) 5-39
flag (CF2) 5-43
interrupt enable (CIE2) 5-41
flag (PF2) 5-43
interrupt enable (PIE2) 5-41
peripheral interface (QSPI) 6-13
flowchart 4-40
timing diagram E-10
register full (RDRF) 6-48
–R–
MOTOROLA
Index-11