MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 374

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.1.3 Glossary of terms used in the CMFI EEPROM Specification
MC68F375
REFERENCE MANUAL
Array block — CMFI array subdivision: a 32-Kbyte contiguous block of information.
Each array block may be erased independently.
BIU — Bus interface unit controls access and operation of the CMFI array through a
standard IMB3 interface.
Burst read — Array read operation that requires 2 clocks for the first data access and
1 clock for the following data accesses.
CMFI — The CDR MoneT FLASH EEPROM for the IMB3.
Erase interlock write — A write to any CMFI array address after initializing the erase
sequence.
Erase margin read — Special burst buffer updates of the CMFI array where the CMFI
EEPROM hardware adjusts the reference of the sense amplifier to check for correct
erase operation. All CMFI array burst buffer updates between the erase interlock write
and clearing the SES bit are erase margin reads.
IM — Integration module.
IMB3 — A motherboard-on-a-chip for embedded controller designs.
Notable features of the bus architecture include: burst data transfers, multiple bus
masters, exception processing support, address space partitioning, multiple interrupt
levels, vectored interrupts, and extendable bus cycles via wait state insertion.
• External 4.75 to 5.25 V V
• Array block 0 enable is selected from one of two sources:
• Data word length of 16 bits.
• Supports IMB3 burst read accesses.
• Software mapping to establish array base address.
• Emulation support
• Low power disable via the integration module.
• Wait states for integration from slower external memory.
— Program pulses from 4.0 µs to 2.73 ms.
— Erase pulses from 4.096 ms to 2.796 s.
— A pin external to the device (EPEB0)
— The inverted state of the CMFI PROTECT bit.
— Contains two separate non-sequential burst buffers.
— Burst buffer size of 32 bytes.
— Burst terminated at end of buffer or by IMB3.
— Support for integration modules with external emulation through a special chip
— Supports internal emulation through memory overlay option.
MHz to 40.0 MHz.
select.
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
PP
program and erase power supply.
Rev. 25 June 03
MOTOROLA
10-4